Octel XC1000, Руководство по обслуживанию

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COMPONENT DESCRIPTIONS
10-5 Edition One XC1000 Service
The CPU communicates with one card at a time. The CPU can send simple
commands, such as resetting a card, setting up data transfer between itself and
another card, or transferring data among cards. The CPU can also send broad-
cast control-bus messages to all cards. For example, the CPU can instruct all
cards to identify themselves.
Data and digitized speech are transferred over the data bus. The CPU selects
the cards for the data transfer. Data is transferred in variable-size bit packets
(up to 64 KB) over the data bus, at a rate of 16 Mbps.
The CPU battery provides backup power to maintain the date and time and
the static-RAM information on the CPU if input power is interrupted. If power
is off for more than 4 hours, the software requires that the time and date be
reset manually before the boot process is complete, even though the battery
could provide power for many years. This software checkpoint is provided to
ensure that the clock time does not drift.
Figure 10-4 shows the status and alarm LEDs on the front edge of the CPU
for a redundant XC1000. A Nonredundant CPU has only the
PWR
and
L9
through L2 LEDs. Table 10-1 describes the function of each LED. During the
system boot process, LEDs L6 through L9 are used for internal diagnostic
testing by the initial program load (IPL). If the CPU fails the diagnostic tests,
the LEDs indicate the reason. Once the system boots,
L6 through L9 have
no significant meaning. Refer to section 6.3.4 for an explanation of the LEDs
lit when the diagnostic tests fail.
Several types of CPUs are available for XC1000. These are discussed in
sections 10.2.1.1 and 10.2.1.2.
10.2.1.1 C10 CPU . The C10 CPU, P/N 244-2004-001, contains 8 MB of RAM. It
replaces the 2-MB CPU, P/N 244-2004-000. Before a C10 CPU can be
installed, the S1 memory-configuration switches, located near the center of
the card, must be set for 8 MB, as shown in Figure 10-5.
For XC1000s at Release 1.5X or newer, the C10 CPU can be upgraded to
16 MB of memory by replacing the eight 1-MB single in-line memory
modules (SIMMs) on the CPU with four higher-capacity 4-MB SIMMs.
(Refer to section 12.7.2 for the procedure). After upgrading the C10 CPU to
16 MB, relabel the CPU with P/N 044-2004-002, revision C.
If the memory upgrade to 16 MB is performed, the C10 CPU must contain
the following EPROMs:
Low-byte EPROM, P/N 039-1272-002, revision 9104 or higher, at
location U9G
High-byte EPROM, P/N 039-1273-002, revision 9104 or higher, at
location U7G.
If these EPROMs are not present, the existing EPROMs must be replaced
with these revision 9104 EPROMs.
SECTION 10.2