NXP Semiconductors LCP43 Series, Руководство пользователя

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1.3 — 6 July 2012 838 of 1269
NXP Semiconductors
UM10503
Chapter 28: LPC43xx State Configurable Timer (SCT)
28.7.8 DMA operation
A DMA controller can be used to write one or more Reload registers, or read one or more
Capture registers, typically at the start of a counter cycle. DMA access to more than one
Reload or Capture register requires that they be consecutive registers. (Nothing else in
the SCT constrains how these registers are assigned and used.)
An event can set a DMA request or set when a counter Match registers are loaded from its
Reload registers, as described in
Section 28.6.14 . The two requests of the SCT can be
used to do the same register access for both counters when UNIFY is 0. Alternatively, one
request can be used for writing Reload registers and the other for reading Capture
registers.
The SCT does not know how many transfers are done for each request, so it cannot
control its DMA requests accordingly.
The two DMA requests are connected to DMABREQ7 and DMABREQ8. Write the number
of registers to be transferred for each request to the TransferSize field in the Channel
Control Register of the DMA channel to which the request is connected. If the Linked List
feature is used, there is a TransferSize value in each Linked List entry. The GPDMA
asserts the DMACCLR signal when that number of transfers has been completed, which
makes the SCT clear the request.
28.7.9 Alternate addressing for match/capture registers
The Match, Reload, Capture, and Capture Control registers are arranged as consecutive
words, with the standard division of each word into two halfwords. When the UNIFY bit is
zero, these two halfwords are related to the L and H counters. Software has the option of
writing words initially to set up both halves of a SCT simultaneously, or writing halfwords to
set up each half separately.
Applications can use a DMA controller to write Reload registers or to read Capture
registers. However, when UNIFY is 0, the addressing of the halfword registers is not
compatible with the requirement of many DMA controllers to use consecutive addresses
for sequential address operation.
Table 675 shows how the second half of the range
occupied by each type of register contains an alternate address map for halfword
accesses to the same registers, which is compatible with DMA that use sequential
address operation. When UNIFY is 1, perform DMA word accesses using standard
offsets.
Table 675. Alternate address map for DMA halfword access
Match register Capture register Standard offset DMA halfword offset
MATCH0_L CAP0_L 0x100 0x180
MATCH0_H CAP0_H 0x102 0x1C0
MATCH1_L CAP1_L 0x104 0x182
MATCH1_H CAP1_H 0x106 0x1C2
... ... ... ...
MATCHREL0_L CAPCTRL0_L 0x200 0x280
MATCHREL0_H CAPCTRL0_H 0x202 0x2C0