UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
443 of 1269
NXP Semiconductors
UM10503
Chapter 20: LPC43xx SD/MMC interface
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CLKDIV @0x08 = 0x0 (bypass of clock divider).
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CLKSRC @0x0C = 0x0
•
CLKENA @0x10 =0x0 or 0x1. This register enables or disables clock for the card and
enables low-power mode, which automatically stops the clock to a card when the card
is idle for more than 8 clocks.
The Module loads each of these registers only when the start_cmd bit and the
Update_clk_regs_only bit in the CMD register are set. When a command is successfully
loaded, the Module clears this bit, unless the Module already has another command in the
queue, at which point it gives an HLE (Hardware Locked Error); for details on HLEs, refer
to "Error Handling".
Software should look for the start_cmd and the Update_clk_regs_only bits, and should
also set the wait_prvdata_complete bit to ensure that clock parameters do not change
during data transfer. Note that even though start_cmd is set for updating clock registers,
the Module does not raise a command_done signal upon command completion.
20.7.4.4 No-Data Command With or Without Response Sequence
To send any non-data command, the software needs to program the CMD register @0x2C
and the CMDARG register @0x28 with appropriate parameters. Using these two
registers, the Module forms the command and sends it to the command bus. The Module
reflects the errors in the command response through the error bits of the RINTSTS
register.
When a response is received - either erroneous or valid - the Module sets the
command_done bit in the RINTSTS register. A short response is copied in Response
Register0, while a long response is copied to all four response registers @0x30, 0x34,
0x38, and 0x3C. The Response3 register bit 31 represents the MSB, and the Response0
register bit 0 represents the LSB of a long response.
For basic commands or non-data commands, follow these steps:
1. Program the Command register @0x28 with the appropriate command argument
parameter.
2. Program the Command register @0x2C with the settings in
3. Wait for command acceptance by cpu. The following happens when the command is
loaded into the Module:
–
Module accepts the command for execution and clears the start_cmd bit in the
CMD register, unless one command is in process, at which point the Module can
load and keep the second command in the buffer.
–
If the Module is unable to load the command - that is, a command is already in
progress, a second command is in the buffer, and a third command is attempted -
then it generates an HLE (hardware-locked error).
–
Check if there is an HLE.
–
Wait for command execution to complete. After receiving either a response from a
card or response time-out, the Module sets the command_done bit in the RINTSTS
register. Software can either poll for this bit or respond to a generated interrupt.
