UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
977 of 1269
NXP Semiconductors
UM10503
Chapter 37: LPC43xx USART0_2_3
The RS485CTRL bit 4 takes precedence over all other mechanisms controlling the
direction control pin.
RS485/EIA-485 driver delay time
The driver delay time is the delay between the last stop bit leaving the TXFIFO and the
de-assertion of the DIR pin. This delay time can be programmed in the 8-bit RS485DLY
register. The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit
times may be used.
RS485/EIA-485 output inversion
The polarity of the direction control signal on the DIR pin can be reversed by programming
bit 5 in the RS485CTRL register. When this bit is set, the direction control pin will be
driven to logic 1 when the transmitter has data waiting to be sent. The direction control pin
will be driven to logic 0 after the last bit of data has been transmitted.
37.7.5 Synchronous mode
When the synchronous receiver/ transmitter feature is configured (USART), the serial
interface is extended with a serial input and output clock and an output enable for
controlling the clock pad.
By default transmission and reception in synchronous mode operates uses the same
protocol as in asynchronous mode. Synchronous mode can be configured using the
Synchronous Mode Control Register. This register allows to control:
•
The direction of the serial clock, i.e. synchronous slave or master mode
•
The sampling edge of the serial clock
•
Two-stage or one stage synchronization of the input serial clock during transmission
•
During synchronous master mode, the clock can be continuous or disabled when in
idle or break mode
•
The transmission of start and stop bits can be omitted. Valid data is identified by a
running clock. Sampling is always done on the falling edge of the serial clock
Data is shifted in the receive shift register at the sampling edge of the serial clock.
37.7.5.1 Synchronous slave mode
This mode is enabled by setting the CSRC bit of the control register to ‘0’. During
synchronous slave mode, an external clock is required that clocks the serial input and
output data. Note that internally, the serial clock is treated as a data signal. Edge detection
on the serial clock is performed to synchronize the serial clock with the USART clock
domain, hence no registers are clocked with the serial clock.
Reception
By default the received character is similar to the character in asynchronous mode. The
serial data stream is kept HIGH when no data is available. During this time it is not
required for the external serial clock to be running. The first bit that will be received is the
start bit. During this time, the external serial clock must be running. The beginning of the
start bit can either be aligned with the rising edge of the serial clock (sampling on the
falling edge) or the falling edge (sampling on the rising edge), see the FES bit in
. When sampling on the rising edge, it is not required that the beginning of the
