UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
404 of 1269
NXP Semiconductors
UM10503
Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller
Little
Little
32
32
1/[7:0]
1/[15:8]
1/[23:16]
1/[31:24]
21
43
65
87
1/[31:0]
87654321
Big
Big
8
8
1/[31:24]
2/[23:16]
3/[15:8]
4/[7:0]
12
34
56
78
1/[31:24]
2/[23:16]
3/[15:8]
4/[7:0]
12121212
34343434
56565656
78787878
Big
Big
8
16
1/[31:24]
2/[23:16]
3/[15:8]
4/[7:0]
12
34
56
78
1/[15:0]
2/[31:16]
12341234
56785678
Big
Big
8
32
1/[31:24]
2/[23:16]
3/[15:8]
4/[7:0]
12
34
56
78
1/[31:0]
12345678
Big
Big
16
8
1/[31:24]
1/[23:16]
2/[15:8]
2/[7:0]
12
34
56
78
1/[31:24]
2/[23:16]
3/[15:8]
4/[7:0]
12121212
34343434
56565656
78787878
Big
Big
16
16
1/[31:24]
1/[23:16]
2/[15:8]
2/[7:0]
12
34
56
78
1/[15:0]
2/[31:16]
12341234
56785678
Big
Big
16
32
1/[31:24]
1/[23:16]
2/[15:8]
2/[7:0]
12
34
56
78
1/[31:0]
12345678
Big
Big
32
8
1/[31:24]
1/[23:16]
1/[15:8]
1/[7:0]
12
34
56
78
1/[31:24]
2/[23:16]
3/[15:8]
4/[7:0]
12121212
34343434
56565656
78787878
Big
Big
32
16
1/[31:24]
1/[23:16]
1/[15:8]
1/[7:0]
12
34
56
78
1/[15:0]
2/[31:16]
12341234
56785678
Big
Big
32
32
1/[31:24]
1/[23:16]
1/[15:8]
1/[7:0]
12
34
56
78
1/[31:0]
12345678
Table 292. Endian behavior
…continued
Source
endian
Destination
endian
Source
width
Destination
width
Source
transfer
no/byte lane
Source data Destination
transfer
no/byte lane
Destination data