Motorola MPC8240, Руководство пользователя

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2-6 MPC8240 Integrated Processor User’s Manual
Signal Overview
2.1.2 Output Signal States during Reset
When a system reset is recognized (assertion of HRST_CPU and HRST_CTRL), the
MPC8240 aborts all current internal and external transactions, and releases all bidirectional
I/O signals to a high-impedance state. See Section 13.2.1, “System Reset,” for a complete
description of the reset functionality.
There are 19 signals that serve alternate functions as reset configuration input signals
during system reset. Their default values and the interpretation of their voltage levels during
reset are described in Section 2.4, “Configuration Signals Sampled at Reset.”
SDMA12 SDRAM address 12 Memory
See Table 6-2
1 O 2.2.2.7
SDMA[11:0] SDRAM address 11–0 Memory 12 O 2.2.2.6
SDRAM_CLK[0:3] SDRAM clock outputs Clock — 4 O 2.2.7.5
SDRAM_SYNC_OUT SDRAM clock output Clock — 1 O 2.2.7.6
SDRAM_SYNC_IN SDRAM feedback clock Clock — 1 I 2.2.7.7
SDRAS SDRAM row address
strobe Memory — 1 O 2.2.2.13
SERR System error PCI — 1 I/O 2.2.1.12
S_FRAME Serial interrupt frame EPIC Control IRQ3 1 I/O 2.2.3.2.4
S_INT Serial interrupt stream EPIC Control IRQ0 1 I 2.2.3.2.1
SMI System management
interrupt System Control — 1 I 2.2.5.5
S_RST Serial interrupt reset EPIC Control IRQ2 1 I/O 2.2.3.2.3
SRESET Soft reset System Control — 1 I 2.2.5.2
STOP Stop PCI — 1 I/O 2.2.1.13
TBEN Time base enable System Control — 1 I 2.2.5.7
TCK JTAG test clock Test — 1 I 2.2.6.2
TDO JTAG test data output Test — 1 O 2.2.6.4
TDI JTAG test data Input Test — 1 I 2.2.6.3
TMS JTAG test mode select Test — 1 I 2.2.6.5
TRDY Target ready PCI — 1 I/O 2.2.1.10
TRIG_IN Watchpoint trigger in System Control 1 I 2.2.5.9.1
TRIG_OUT Watchpoint trigger out System Control 1 O 2.2.5.9.2
TRST JTAG test reset Test — 1 I 2.2.6.6
WE Write enable Memory — 1 O 2.2.2.5
1
The MPC8240 samples these signals at the negation of reset to determine the reset configuration. After they
are sampled, they assume their normal functions. See Section 2.4, “Configuration Signals Sampled at Reset,”
for more information about their function during reset.
Table 2-1. MPC8240 Signal Cross Reference (Continued)
Signal Signal Name Interface
Alternate
Function (s)
Pins I/O Section #