Motorola MPC8240, Руководство пользователя

Страница: 481 / 642

Chapter 15. Debug Features 15-1
Chapter 15
Debug Features
The MPC8240 provides several features to aid in starting-up and debugging the system.
This chapter describes the following functions:
• Address attributes signals—Identification of the source and type of transaction
currently being performed on either the PCI or memory interface.
• Debug address signals—Supplementation of the DRAM column address and chip
select signals, allowing the system to reconstruct the corresponding physical address
on the internal peripheral logic bus in a single cycle.
• MIV signal—Marking of valid address and data bus cycles on the memory bus.
• Memory data path error injection/capture—Injection of multi-bit stuck-at faults onto
the peripheral logic or memory data/parity buses and capture the data/parity upon
the receipt of an ECC or parity error
• JTAG/testing support
15.1 Debug Register Summary
The only debug registers in the MPC8240 are the six memory data path diagnostic registers
consisting of three error injection mask registers and three error capture monitor registers.
mapped as follows:
• Embedded utilities memory block (EUMBBAR) for local bus accesses at offsets
0xF_F000 to 0xF_FFFF
• Embedded utilities peripheral control and status registers (PCSRBAR) for PCI bus
accesses at offsets 0xF00 to 0xFFF
Note that this data path diagnostic register space is also shared with the watchpoint registers
described in Chapter 16, “Programmable I/O and Watchpoint.” The offsets to individual
registers are defined in Table 15-1.The memory data path error injection/capture
functionality is described in more detail in Section 15.5, “Memory Data Path Error
Injection/Capture.” Note that while these registers are mapped from local bus offset
0xF_F000 to 0xF_F014 (PCI offset 0xF00 to 0xF14), the watchpoint registers are mapped
from the local bus offset 0xF_F018 though 0xF_F042 (PCI offset 0xF18 to 0xF42).