Motorola MPC8240, Руководство пользователя

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6-16 MPC8240 Integrated Processor User’s Manual
SDRAM Interface Operation
6.2.4 SDRAM Power-On Initialization
At system reset, initialization software must set up the programmable parameters in the
memory interface configuration registers. These include the memory boundary registers,
the memory banks enable register, the memory page mode register, and the memory control
configuration registers (MCCRs). See Chapter 4, “Configuration Registers,” for more
detailed descriptions of the configuration registers. The programmable parameters relevant
to the SDRAM interface are:
• Memory bank starting and ending addresses (memory boundary registers)
• Memory bank enables
• PGMAX—maximum activate to precharge interval (also called row active time or
t
RAS
)
• SREN—self refresh enable
• RAM_TYPE—SDRAM, FPM or EDO
• PCKEN—parity check enable
• Row address configuration for each bank
• INLINE_PAR_NOT_ECC select between ECC or parity on the memory bus for
in-line buffer mode only.
• WRITE_PARITY_CHK—enable write path parity error reporting
• INLRD_PARECC_CHK_EN—enable in-line read path ECC or parity error
reporting
• REFINT—interval between refreshes
• RSV_PG—reserves a page register, thus allowing only three simultaneously open
pages
• RMW_PAR—enables read-modify-write parity operation
• BSTOPRE—burst to precharge interval (page open interval)
• REFREC—refresh recovery interval from last refresh clock cycle to activate
command
• RDLAT—data latency from read command
• PRETOACT—precharge to activate interval
• ACTOPRE—activate to precharge interval
• BUF_TYPE—selects the data path buffer mode (flow-through, registered, in-line)
• REGDIMM—enables registered DIMM mode
• SDMODE—mode register data to be transferred to SDRAM array by the MPC8240
—specifies CAS latency, wrap type, and burst length
• ACTORW—activate to read or write interval