Motorola MPC8240, Руководство пользователя

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2-26 MPC8240 Integrated Processor User’s Manual
Detailed Signal Descriptions
2.2.5.1 Hard Reset
The two hard reset signals on the MPC8240 (HRST_CPU and HRST_CTRL) must be
asserted and negated together to guarantee normal operation. Together, HRST_CPU and
HRST_CTRL cause the MPC8240 to abort all current internal and external transactions,
and set all registers to their default values. Although HRST_CPU and HRST_CTRL must
be asserted together, they may be asserted completely asynchronously with respect to all
other signals. See Section 13.2.1, “System Reset,” for a complete description of the reset
functionality.
2.2.5.1.1 Hard Reset (Processor) (HRST_CPU)—Input
The following describes the state meaning and timing for the HRST_CPU input signal.
State Meaning Asserted/Negated—See Section 2.1.2, “Output Signal States during
Reset,” and Section 2.4, “Configuration Signals Sampled at Reset,”
for more information on the interpretation of the other MPC8240
signals during reset.
Timing Comments Assertion/Negation—See the MPC8240Hardware Specification for
specific timing information of these signals and the reset
configuration signals.
2.2.5.1.2 Hard Reset (Peripheral Logic) (HRST_CTRL)—Input
The following describes the state meaning and timing for the HRST_CTRL input signal.
State Meaning Asserted/Negated—See Section 2.1.2, “Output Signal States during
Reset”, and Section 2.4, “Configuration Signals Sampled at Reset,”
for more information on the interpretation of the other MPC8240
signals during reset.
Timing Comments Assertion/Negation—See the MPC8240 Hardware Specification for
specific timing information of these signals and the reset
configuration signals.
2.2.5.2 Soft Reset (SRESET)—Input
The assertion of the soft reset input signal causes the same actions as the assertion of the
internal sreset signal by the EPIC unit. A soft reset is recoverable, provided that in
attempting to reach a recoverable state, the processor does not encounter a machine check
condition. A soft reset exception is third in priority, following a hard reset and machine
check.
State Meaning Asserted/Negated—When SRESET is asserted, the processor core
attempts to reach a recoverable state by allowing the next instruction
to either complete or cause an exception, blocking the completion of
subsequent instructions, and allowing the completed store queue to
drain. Unlike a hard reset, no registers or latches are initialized;
however, the instruction cache is disabled (HID0[ICE] = 0].