Motorola MPC8240, Руководство пользователя

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8-4 MPC8240 Integrated Processor User’s Manual
DMA Operation
destination addresses are valid PCI or local memory addresses. If MCCR2[RMW_PAR] is
cleared, there is no penalty for misaligned transfers. As such, misaligned transfers do not
affect bandwidth.
All local memory read operations are non-pipelined cache line reads (32 bytes). The DMA
controller selects the valid data bytes within a cache line when storing in its queue. Writing
to local memory depends on the destination address and the number of bytes transferred.
The DMA controller attempts to write cache lines (non-pipelined) if the destination address
is aligned on a 32-byte boundary. Otherwise, partial cache line writes are performed.
PCI memory read operations depend on the PRC bits in the DMR, the source address, and
the number of bytes transferred. The DMA controller attempts to read a cache line (32
bytes) whenever possible. All PCI reads are whole beat reads (4 bytes) except when the
DMR[SAHE] bit is set (see Table 8-3). Internally, the DMA engine determines the valid
bytes within a read and stores them into the queue accordingly.
Writing to PCI memory depends on the destination address and the number of bytes
transferred. PCI Write-and-Invalidate operations are performed only if a full cache line is
being transferred, the PCI command status register (PCSR) bit 4 (memory write and
invalidate) is set, and the PCI cache line size register is set to 0x08 (32-byte cache size).
Otherwise, write operations are performed.
The internal DMA protocols operate on a cache line basis, so the MPC8240 always
attempts to perform transfers that are the size of a cache line. The only possible exceptions
are the first or last transfer. To further enhance performance, the protocols also allow for
multiple-cache-line streaming operation in which more than one cache line can be
transferred at one time. Therefore, maximum performance is achieved when the initial
address of a DMA transfer is aligned to a cache-line boundary.
8.3.1 DMA Direct Mode
In direct mode, the DMA controller does not read descriptors from memory but instead uses
the current parameters in the DMA registers to start a DMA process. The DMA transfer is
finished after all bytes specified in the BCR have been transferred, or an error condition has
occurred. The initialization steps for a DMA transfer in direct mode are as follows:
1. Poll the CB in the DSR to make sure the DMA channel is idle.
2. Initialize the SAR, DAR, and BCR.
3. Initialize the CTT bit in the CDAR to indicate the type of transfer.
4. Initialize the CTM bit in the DMR to indicate direct mode. Other control parameters
in the DMR can also be initialized here, if necessary.
5. Clear and then set the CS bit in the DMR to start the DMA transfer.
Note that the DMA registers used for setting up the descriptors in chaining mode also have
some implications in direct mode.