Motorola MPC8240, Руководство пользователя

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5-8 MPC8240 Integrated Processor User’s Manual
PowerPC Processor Core Features
5.2.4.4 System Register Unit (SRU)
The SRU executes various system-level instructions, including condition register logical
operations and move to/from special-purpose register instructions, and integer
add/compare instructions. Because SRU instructions affect modes of processor operation,
most SRU instructions are completion-serialized. That is, the instruction is held for
execution in the SRU until all prior instructions issued have completed. Results from
completion-serialized instructions executed by the SRU are not available or forwarded for
subsequent instructions until the instruction completes.
5.2.5 Completion Unit
The completion unit tracks instructions from dispatch through execution, and then retires,
or completes them in program order. Completing an instruction commits the processor core
to any architectural register changes caused by that instruction. In-order completion ensures
the correct architectural state when the processor core must recover from a mispredicted
branch or any exception.
Instruction state and other information required for completion is kept in a first-in-first-out
(FIFO) queue of five completion buffers. A single completion buffer is allocated for each
instruction once it enters the dispatch unit. An available completion buffer is a required
resource for instruction dispatch; if no completion buffers are available, instruction
dispatch stalls. A maximum of two instructions per cycle are completed in order from the
queue.
5.2.6 Memory Subsystem Support
The processor core supports cache and memory management through separate instruction
and data MMUs (IMMU and DMMU). The processor core also provides dual 16-Kbyte
instruction and data caches, and an efficient peripheral bus interface to facilitate access to
main memory and other bus subsystems. The memory subsystem support functions are
described in the following subsections.
5.2.6.1 Memory Management Units (MMUs)
The processor core’s MMUs support up to 4 Petabytes (2
52
) of virtual memory and
4 Gbytes (2
32
) of physical memory (referred to as real memory in the PowerPC architecture
specification) for instructions and data. The MMUs also control access privileges for these
spaces on block and page granularities. Referenced and changed status is maintained by the
processor for each page to assist implementation of a demand-paged virtual memory
system. A key bit is implemented to provide information about memory protection
violations prior to page table search operations.
The LSU calculates effective addresses for data loads and stores, performs data alignment
to and from cache memory, and provides the sequencing for load and store string and
multiple word instructions. The instruction unit calculates the effective addresses for
instruction fetching.