Motorola MPC8240, Руководство пользователя

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Appendix E. Processor Core Register Summary E-25
MPC8240-Specific Registers
8 DOZE Doze mode enable. Operates in conjunction with MSR[POW]
1
0 Processor doze mode disabled.
1 Processor doze mode enabled. Doze mode is invoked by setting MSR[POW] while this bit is
set. In doze mode, the PLL, time base, and snooping remain active.
9 NAP Nap mode enable—Operates in conjunction with MSR[POW]
1
0 Processor nap mode disabled
1 Processor nap mode enabled. Nap mode is invoked by setting MSR[POW] while this bit is set.
When this occurs, the processor indicates that it is ready to enter nap mode. If the peripheral
logic determines that the processor may enter nap mode (no more snooping of the internal
buffers is required), the processor enters nap mode after several processor clocks. In nap
mode, the PLL and the time base remain active.
Note that the MPC8240 asserts the QACK output signal depending on the power-saving state
of the peripheral logic, and not on the power-saving state of the processor core.
10 SLEEP Sleep mode enable—Operates in conjunction with MSR[POW]
1
0 Processor sleep mode disabled.
1 Processor sleep mode enabled—Sleep mode is invoked by setting MSR[POW] while this bit
is set. When this occurs, the processor indicates that it is ready to enter sleep mode. If the
peripheral logic determines that the processor may enter sleep mode (no more snooping of
the internal buffers is required), the processor enters sleep mode after several processor
clocks. At this point, the system logic may turn off the PLL by first configuring PLL_CFG[0–4]
to PLL bypass mode, and then disabling the internal sys_logic-clk signal.
Note that the MPC8240 asserts the QACK output signal depending on the power-saving state
of the peripheral logic, and not on the power-saving state of the processor core.
11 DPM Dynamic power management enable
1
0 Processor dynamic power management is disabled.
1 Functional units enter a low-power mode automatically if the unit is idle. This does not affect
operational performance and is transparent to software or any external hardware.
12–14 — Reserved
15 NHR Not hard reset (software-use only)—Helps software distinguish a hard reset from a soft reset.
0 A hard reset occurred if software had previously set this bit.
1 A hard reset has not occurred. If software sets this bit after a hard reset, when a reset occurs
and this bit remains set, software can detect that it was a soft reset.
16 ICE Instruction cache enable
2
0 The instruction cache is neither accessed nor updated. All pages are accessed as if they
were marked cache-inhibited (WIM = X1X). Potential cache accesses from the bus (snoop
and cache operations) are ignored. In the disabled state for the L1 caches, the cache tag
state bits are ignored, and all accesses are propagated to the bus as single-beat transactions.
For these transactions, however, the processor reflects the original state of the I bit (from the
MMU) to the peripheral logic block, regardless of cache disabled status.
ICE is zero at power-up.
1 The instruction cache is enabled
17 DCE Data cache enable
2
0 The data cache is neither accessed nor updated. All pages are accessed as if they were
marked cache-inhibited (WIM = X1X). Potential cache accesses from the bus (snoop and
cache operations) are ignored. In the disabled state, the cache tag state bits are ignored and
all accesses are propagated to the bus as single-beat transactions.
For those transactions, however, the processor reflects the original state of the I bit (from the
MMU) to the peripheral logic block, regardless of cache disabled status.
DCE is zero at power-up.
1 The data cache is enabled.
Table E-20. HID0 Field Descriptions (Continued)
Bits Name Description