Motorola MPC8240, Руководство пользователя

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Chapter 6. MPC8240 Memory Interface 6-3
Memory Interface Signal Summary
Figure 6-1. Block Diagram for Memory Interface
6.1 Memory Interface Signal Summary
Table 6-1 summarizes the memory interface signals. Note that some signals function
differently depending on the type of memory system the MPC8240 is configured to support.
Table 6-1. Memory Interface Signal Summary
Signal Name Signal Name Alternate Function Pins I/O
RAS[0:7] DRAM row address strobe 0–7 CS[0:7] 8 O
CAS[0:7] DRAM column address strobe 0–7 DQM[0:7] 8 O
CS[0:7] SDRAM chip select 0–7 RAS[0:7] 8 O
DQM[0:7] SDRAM data mask in/out 0–7 CAS[0:7] 8 O
WE Write enable — 1 O
RCS1
RCS0
FOE
AS
WE
CAS/DQM[0:7]
RAS/CS[0:7]
PAR[0:7]
CKE
SDCAS
SDRAS
Memory
Controller
Interface
SDRAM RMW Parity
ROM/Flash
MDH[0:31]
MDL[0:31]
PCI
Configuration
Registers
Parity
64-bit ECC
Central
Control
Unit
ECC or Parity
Memory Control
DLL
SDRAM _CLK[0:3]
SDRAM_SYNC_OUT
SDRAM_SYNC_IN
SDBA[1:0]
Interface logic
Error Injection/
Capture
PCI
Clock-In
Processor
PLL
32-bit
AR[19:12]
64-bit In-Line ECC
Address
Path
Bus
Interface
Peripheral
Logic Bus
PCI Bus
32- or 64-bit
Data Bus
32-bit
Address Bus
Memory Clock
Processor
PLL
Memory Clock
Data path
Data path
SDMA[12:0]
Core
Processor
Peripheral
PLL
Logic
Port X
8-bit
ROM/Flash
Port X
64-bit
FPM/EDO
RMW Parity
Parity
64-bit ECC
DRAM
DMA 1
Queue
64 bytes
DMA 0
Queue