Motorola MPC8240, Руководство пользователя

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Appendix A. Address Map A A-1
Appendix A
Address Map A
The MPC8240 supports two address maps. The preferred address map, map B, is described
in Chapter 3, “Address Maps.” This appendix describes address map A.
Address map A conforms to the now-obsolete PowerPC reference platform (PReP)
specification. Support for address map A is provided solely for backward compatibility
with MPC106-based systems that used the PReP address map. It is strongly recommended
that new designs use map B and existing designs be revised to use map B because map A
may not be supported in future devices.
A.1 Address Space for Map A
The address space of map A is divided into four areas—local memory, PCI I/O, PCI
memory, and system ROM space. Table A-1, Figure A-2, and Table A-3 show separate
views of address map A for the processor core, a PCI memory device, and a PCI I/O device,
respectively. When configured for map A, the MPC8240 translates addresses across the
internal peripheral logic bus and the external PCI bus as shown in Figure A-1 through
Figure A-3.
Table A-1. Address Map A—Processor View
Processor Core Address Range
PCI Address Range Definition
Hex Decimal
0000_0000 3FFF_FFFF 0 1G - 1 No PCI cycle Local memory space
4000_0000 7FFF_FFFF 1G 2G - 1 No PCI cycle Reserved
8000_0000 807F_FFFF 2G 2G + 8M - 1 0000_0000–007F_FFFF PCI I/O space
1,2
8080_0000 80FF_FFFF 2G + 8M 2G + 16M - 1 0080_0000–00FF_FFFF PCI configuration
direct access
3
8100_0000 BF7F_FFFF 2G + 16M 3G - 8M - 1 0100_0000–3F7F_FFFF PCI I/O space
BF80_0000 BFFF_FFEF 3G - 8M 3G - 16 - 1 3F80_0000–3FFF_FFEF Reserved
BFFF_FFF0 BFFF_FFFF 3G - 16 3G - 1 3FFF_FFF0–3FFF_FFFF PCI interrupt
acknowledge
C000_0000 FEFF_FFFF 3G 4G - 16M - 1 0000_0000–3EFF_FFFF PCI memory space
FF00_0000 FFFF_FFFF 4G - 16M 4G - 1 FF00_0000–FFFF_FFFF
4
ROM space
4