Motorola MPC8240, Руководство пользователя

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4-40 MPC8240 Integrated Processor User’s Manual
Error Handling Registers
Figure 4-26 shows the PCI bus error status register.
Figure 4-26. PCI Bus Error Status Register—0xC7
Table 4-35 describes the bits of the PCI bus error status register.
The processor/PCI error address register maintains address bits for either the processor bus
or the PCI bus transaction that generated an error as shown in Figure 4-27.
Figure 4-27. Processor/PCI Error Address Register—0xC8
Table 4-36 describes the bits of processor/PCI error address register.
Table 4-35. Bit Settings for PCI Bus Error Status Register—0xC7
Bits Name
Reset
Value
Description
7–5 — 000 Reserved
4 MPC8240
master/target status 0 MPC8240 master/target status
0 MPC8240 is the PCI master.
1 MPC8240 is the PCI target.
3–0 C/BE[3:0] 0000 These bits maintain a copy of C/BE[3:0]. When a PCI bus error is
detected, these bits are latched until all error flags are cleared.
Table 4-36. Bit Settings for Processor/PCI Error Address Register—0xC8
Bits Name
Reset
Value
Description
31–24
Error address 0x00 A[24:31] or AD[7:0]—Dependent on whether the error is a processor bus error or
a PCI bus error. When an error is detected, these bits are latched until all error
flags are cleared.
23–16 0x00 A[16:23] or AD[15:8]—(Dependent on whether the error is a processor bus error
or a PCI bus error. When an error is detected, these bits are latched until all error
flags are cleared.
15–8 0x00 A[8:15] or AD[23:16]—Dependent on whether the error is a processor bus error
or a PCI bus error. When an error is detected, these bits are latched until all error
flags are cleared.
7–0 0x00 A[0:7] or AD[31:24]—Dependent on whether the error is a processor bus error or
a PCI bus error. When an error is detected, these bits are latched until all error
flags are cleared.
0 0 0 C/BE[3:0]
7 5 4 3 0
Reserved
Master/Target Status
MPC8240
Error Address
31 0