Motorola MPC8240, Руководство пользователя

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Chapter 9. Message Unit (with I
2
O) 9-19
I
2
O Interface
Table 9-20 shows the bit settings for the OFTPR.
9.3.4.2.9 Outbound Post_FIFO Head Pointer Register (OPHPR)
The processor core posts MFAs to the outbound post_list FIFO pointed to by the outbound
post_FIFO head pointer register (OPHPR). The processor core is responsible for updating
the contents of OPHPR. Figure 9-17 shows the bits of the OPHPR.
Figure 9-17. Outbound Post_FIFO Head Pointer Register (OPHPR)
Table 9-21 shows the bit settings for the OPHPR.
9.3.4.2.10 Outbound Post_FIFO Tail Pointer Register (OPTPR)
PCI masters pick up posted MFAs from the outbound post_list FIFO pointed to by the
outbound post_FIFO tail pointer register (OPTPR). The actual PCI reads of MFAs are
performed through the outbound FIFO queue port register (OFQPR). The MPC8240
automatically increments the OPTP value after every read from OFQPR.
Table 9-20. OFTPR Field Descriptions—Offset 0x0_0148
Bits Name
Reset
Value
R/W Description
31–20 QBA All 0s R Queue base address. When read, this field returns the contents of QBAR[31–20].
19–2 OFTP All 0s RW Outbound free_FIFO tail pointer. The processor maintains the local memory offset
of the tail pointer of the outbound free_list FIFO in this field.
1–0 — 00 R Reserved
Table 9-21. OPHPR Field Descriptions—Offset 0x0_0150
Bits Name
Reset
Value
R/W Description
31–20 QBA All 0s R Queue base address. When read, this field returns the contents of QBAR[31–20].
19–2 OPHP All 0s RW Outbound post_FIFO head pointer. The processor maintains the local memory
offset of the head pointer of the outbound post_list FIFO in this field.
1–0 — 00 R Reserved
QBA OPHP 0 0
31 20 19 2 1 0
Reserved