Motorola MPC8240, Руководство пользователя

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12-10 MPC8240 Integrated Processor User’s Manual
Internal Arbitration
The priority between simultaneous accesses from the external PCI bus and the DMA
controller to the shared processor/memory data bus is controlled by the arbiter shown in
Figure 12-5 as follows:
• External PCI masters always have greater priority than DMA accesses.
• The priority between DMA channels 0 and 1 is round-robin.
If a DMA channel is currently accessing local memory, then accesses from external PCI
devices are retried. Rearbitration within this arbiter between the DMA channels and
external PCI masters occurs at DMA transaction boundaries. DMA transaction boundaries
for some DMA-initiated transactions are affected by the setting of the DMR[LMDC] value
as described in the following subsections. Also see Section 8.7.1, “DMA Mode Registers
(DMRs),” for detailed information about DMR[LMDC].
12.2.1.1 DMA Transaction Boundaries for Memory/Memory Transfers
DMA transaction boundaries for local memory to local memory transfers occur as follows:
• When DMR[LMDC] is 0b00
— After each cache line write for DMA writes to local memory
— After up to two cache line reads for DMA reads from local memory
• When DMR[LMDC] is nonzero, DMA transaction boundaries occur after the
transfer of a single cache line for both reads and writes to local memory.
Note that depending on the timing of an incoming PCI transfer, if a DMA channel is
performing local memory to local memory transfers, the external PCI master may be
repeatedly retried. Aside from affecting the DMA transaction boundaries, the value of the
DMR[LMDC] also increases the time delay between subsequent DMA accesses to local
memory. To reduce the occurrence of PCI retries in this case, software can increase the
value of the DMR[LMDC] value causing more latency in between DMA accesses to local
memory, and giving a greater probability that the PCI access will gain access to the
processor/memory data bus.
12.2.1.2 DMA Transaction Boundaries for Memory to PCI Transfers
DMA transaction boundaries for local memory to PCI transfers occur as follows:
• When DMR[LMDC] is 0b00, DMA transaction boundaries occur after the
streaming (reads) of up to 4 Kbytes from local memory.
• When DMR[LMDC] is nonzero, DMA transaction boundaries occur after the
transfer of a single cache line for reads from local memory.
In order for a DMA channel to stream (up to 4 Kbytes) from local memory to the PCI bus,
the PCI bus must be available to sustain the streaming. Note that the latency timer
parameter in the PCI latency timer register (PLTR) can affect the streaming of data to the
PCI bus. If the latency timer is set to be a shorter period than the time required to transfer