Motorola MPC8240, Руководство пользователя

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9-16 MPC8240 Integrated Processor User’s Manual
I
2
O Interface
Table 9-15 shows the bit settings for the IFHPR.
9.3.4.2.4 Inbound Free_FIFO Tail Pointer Register (IFTPR)
PCI masters pick up free MFAs from the inbound free_list FIFO pointed to by the inbound
free_FIFO tail pointer register (IFTPR). The actual PCI reads of MFAs are performed
through the inbound FIFO queue port register (IFQPR). The MPC8240 automatically
increments the IFTP value after every read from IFQPR. Figure 9-12 shows the bits of the
IFTPR.
Figure 9-12. Inbound Free_FIFO Tail Pointer Register (IFTPR)
Table 9-16 shows the bit settings for the IFTPR.
9.3.4.2.5 Inbound Post_FIFO Head Pointer Register (IPHPR)
PCI masters post MFAs to the inbound post_list FIFO pointed to by the inbound post_FIFO
head pointer register (IPHPR). The actual PCI writes are performed through the inbound
FIFO queue port register (IFQPR). The MPC8240 automatically increments the IPHP value
after every write to IFQPR. Figure 9-13 shows the bits of the IPHPR.
Table 9-15. IFHPR Field Descriptions—Offset 0x0_0120
Bits Name
Reset
Value
R/W Description
31–20 QBA All 0s R Queue base address. When read, this field returns the contents of QBAR[31–20].
19–2 IFHP All 0s RW Inbound free_FIFO head pointer. The processor maintains the local memory offset
of the head pointer of the inbound free _list FIFO in this field.
1–0 — 00 R Reserved
Table 9-16. IFTPR Field Descriptions—Offset 0x0_0128
Bits Name
Reset
Value
R/W Description
31–20 QBA All 0s R Queue base address. When read, this field returns the contents of QBAR[31–20].
19–2 IFTP All 0s RW Inbound free_FIFO tail pointer. Maintains the local memory offset of the tail pointer
of the inbound free _list FIFO.
1–0 — 00 R Reserved
QBA IFTP 0 0
31 20 19 2 1 0
Reserved