Motorola MPC8240, Руководство пользователя

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5-10 MPC8240 Integrated Processor User’s Manual
Programming Model
When the processor is configured with a 32-bit data bus, memory accesses on the peripheral
logic bus interface allow transfer sizes of 8, 16, 24, or 32 bits in one bus clock cycle. Data
transfers occur in either single-beat transactions, or two-beat or eight-beat burst
transactions, with a single-beat transaction transferring as many as 32 bits. Single- or
double-beat transactions are caused by noncached accesses that access memory directly
(that is, reads and writes when caching is disabled, caching-inhibited accesses, and stores
in write-through mode). Eight-beat burst transactions, which always transfer an entire
cache line (32 bytes), are initiated when a line is read from or written to memory.
When the peripheral logic bus interface is configured with a 64-bit data bus, memory
accesses allow transfer sizes of 8, 16, 24, 32, or 64 bits in one bus clock cycle. Data transfers
occur in either single-beat transactions or four-beat burst transactions. Single-beat
transactions are caused by noncached accesses that access memory directly (that is, reads
and writes when caching is disabled, caching-inhibited accesses, and stores in
write-through mode). Four-beat burst transactions, which always transfer an entire cache
line (32 bytes), are initiated when a line is read from or written to memory.
5.2.6.3.3 Peripheral Logic Bus Frequency
The core can operate at a variety of frequencies allowing the designer to trade off
performance for power consumption. The processor core is clocked from a separate PLL,
which is referenced to the peripheral logic PLL. This allows the microprocessor and the
peripheral logic to operate at different frequencies while maintaining a synchronous bus
interface.
5.3 Programming Model
The following subsections describe the PowerPC instruction set and addressing modes in
general.
5.3.1 Register Set
This section describes the register organization in the processor core as defined by the three
programming environments of the PowerPC architecture—the user instruction set
architecture (UISA), the virtual environment architecture (VEA), and the operating
environment architecture (OEA), as well as the MPC8240 core implementation-specific
registers. Full descriptions of the basic register set defined by the PowerPC architecture are
provided in Chapter 2, “PowerPC Register Set,” in The Programming Environments
Manual.
The PowerPC architecture defines register-to-register operations for all computational
instructions. Source data for these instructions is accessed from the on-chip registers or is
provided as an immediate value embedded in the opcode. The three-register instruction
format allows specification of a target register distinct from the two source registers, thus
preserving the original data for use by other instructions and reducing the number of