Motorola MPC8240, Руководство пользователя

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9-8 MPC8240 Integrated Processor User’s Manual
I
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O Interface
9.3.3.1.1 Inbound Free_List FIFO
The inbound free_list FIFO holds the list of empty inbound MFAs. The external PCI master
reads the inbound FIFO queue port register (IFQPR) which returns the MFA pointed to by
the inbound free_FIFO tail pointer register (IFTPR). The MPC8240’s I
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O unit then
automatically increments the value in IFTPR.
If the inbound free_list FIFO is empty (no free MFA entries), the unit returns
0xFFFF_FFFF.
9.3.3.1.2 Inbound Post_List FIFO
The inbound post_list FIFO holds MFAs that are posted to the processor core from external
PCI masters. PCI masters external to the MPC8240 write to the head of the FIFO by writing
the MFA to the inbound FIFO queue port register (IFQPR). The I
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O unit transfers the MFA
to the location pointed to by the inbound post_FIFO head pointer register (IPHPR).
After the MFA is written to the FIFO, the MPC8240’s I
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O unit automatically increments
the value in IPHPR to set up for the next message. In addition, an interrupt is generated to
the processor core through the EPIC unit (provided the interrupt is not masked). The
inbound post queue interrupt bit in the inbound message interrupt status register
(IMISR[IPQI]) is set to indicate the condition. The processor core should clear the interrupt
bit as part of the interrupt handler and read the message pointed to by the MFA located in
the IPTPR. After the message has been read, the interrupt software must explicitly
increment the value in IPTPR.
When the processor is done using the message, it must return the message to the inbound
free_list FIFO.
9.3.3.2 Outbound FIFOs
The I
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O specification defines two outbound FIFOs—an outbound post_list FIFO and an
outbound free_list FIFO. The outbound FIFOs are used to send messages from the
processor core to a remote host processor.
9.3.3.2.1 Outbound Free_List FIFO
The outbound free_list FIFO holds the MFAs of the empty outbound message locations in
local memory. When the processor core is ready to send an outbound message, it obtains
MFA by reading the OFTPR; then it writes the message into the message frame. The
OFTPR is managed by the processor core.
When an external PCI master is done using a message posted in the outbound post_list
FIFO and needs to return the MFA to the free list, it writes to the outbound FIFO queue port
register (OFQPR). The MPC8240 I
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O unit then automatically writes the MFA to the
outbound free_FIFO head pointer register (OFHPR). This, in turn causes the value in
OFHPR to be automatically incremented.