Intel
®
81341 and 81342 I/O Processors
December 2007
Developer’s Manual
Order Number: 315037-002US
999
Clocking and Reset—Intel
®
81341 and 81342
ATUE
The ATUE does not participate in the IB Reset handshake.
However the affect on the ATUE varies depending on the
PCIE_RC#
strap.
End Point Mode (
PCIE_RC#
= 1):
An Internal Bus Reset does not reset the ATUE when
operating as an endpoint.
Root Complex Mode (
PCIE_RC#
= 0)
No special requirements, the ATUE can be reset at anytime.
This reset includes the configuration space.
Note:
While the ATUX must take special requirements to
prevent corrupting the PCI bus, the PCI Express link
is a point-to-point interface so no precautions need
to be taken before resetting the link.
End Point Mode:
No affect on ATUE logic.
All ATUX Configuration Registers
retain their current values.
Root Complex Mode:
Entire ATUX is reset, including
Configuration Registers. However,
sticky bits in the Configuration
Space are not reset.
MCU
MCU cannot be reset until the powerfail sequence completes. Clear all interrupts and reset MMRs
to default value
MU
MU can be reset at any time
PCI Configuration registers and
MSI-X memory registers are
preserved.
All other MMRs and logic are reset
to their default values.
All Other
Units
No special requirements
Clear all interrupts and reset MMRs
and logic to default value
Table 631. Internal Bus Reset Summary (Sheet 2 of 2)
Unit
Preparation for Reset
Reset Status