70
Interrupt Source
Origin of
Interrupt
Source
Vector
Number
Vector
Address
*
IPR
Priority
DTC
Activa-
tion
DMAC
Activa-
tion
SWDTEND (software-
activated data transfer
end)
DTC
32
H'0080
IPRE14–
IPRE12
High
—
WOVI (interval timer)
Watchdog
timer
33
H'0084
IPRE10–IPRE8
—
—
Reserved
—
34
H'0088
IPRE6–IPRE4
—
—
CMI (compare match)
Refresh
controller
35
H'008C
IPRE2–IPRE0
—
—
Reserved
—
36
H'0090
IPRF14–IPRF12
—
—
37
H'0094
—
—
ADI (A/D conversion end)
A/D
38
H'0098
IPRF10–IPRF8
Reserved
—
39
H'009C
—
—
TGI0A (TGR0A input
capture/compare match)
TPU
channel 0
40
H'00A0
IPRF6–IPRF4
TGI0B (TGR0B input
capture/compare match)
41
H'00A4
—
TGI0C (TGR0C input
capture/compare match)
42
H'00A8
—
TGI0D (TGR0D input
capture/compare match)
43
H'00AC
—
TCI0V (overflow 0)
44
H'00B0
—
—
Reserved
—
45
H'00B4
—
—
46
H'00B8
47
H'00BC
TGI1A (TGR1A input
capture/compare match)
TPU
channel 1
48
H'00C0
IPRF2–IPRF0
TGI1B (TGR1B input
capture/compare match)
49
H'00C4
—
TCI1V (overflow 1)
50
H'00C8
—
—
TCI1U (underflow 1)
51
H'00CC
—
—
TGI2A (TGR2A input
capture/compare match)
TPU
channel 2
52
H'00D0
IPRG14–
IPRG12
TGI2B (TGR2B input
capture/compare match)
53
H'00D4
—
TCI2V (overflow 2)
54
H'00D8
—
—
TCI2U (underflow 2)
55
H'00DC
Low
—
—
Содержание H8S/2670
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