336
5.19.15
Port G
RPORG
*
R
S
PG0DDR
C
Q
D
Modes 1, 2, 5, 6
Set
Modes 4, 7
Reset
WDDRG
S
PFCR0
CS0E
C
Q
D
Set
WPFCR0
PG0
RDRG
RPFCR0
CS
WDDRG: Write to PGDDR
WDRG:
Write to PGDR
WPFCR0: Write to PFCR0
RPORG: Read port G
RDRG: Read
PGDR
RPFCR0: Read PFCR0
Note: * Output enable signal
Modes
1, 2, 4, 5, 6
Mode 7
EXPE
CS
System controller
Bus controller
R
PG0DR
C
Q
D
Reset
WDRG
Internal data bus
Figure 5.58 Port G Block Diagram (a) (Pin PG0)
Содержание H8S/2670
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