102
CSACRH
Bits 7 to 0—
CS
and Address Signal Assertion Period Control 1 (CSXH7 to CSXH0): These
bits specify whether or not the T
h
cycle shown in figure 4.3 is to be inserted. When an area for
which the CSXHn bit is set to 1 is accessed, a T
h
state, in which only the
CSn
and address signals
are asserted, is inserted before the normal access cycle.
A one-state T
h
cycle is inserted regardless of 2-state or 3-state access designation, or the number of
program waits.
Bit n
CSXHn
Description
0
In area n basic bus interface access, the
CSn
and address assertion period (T
h
) is
not extended
(Initial value)
1
In area n basic bus interface access, the
CSn
and address assertion period (T
h
) is
extended
(n = 7 to 0)
CSACRL
Bits 7 to 0—
CS
and Address Signal Assertion Period Control 2 (CSXT7 to CSXT0): These
bits specify whether or not the T
t
cycle shown in figure 4.3 is to be inserted. When an area for
which the CSXTn bit is set to 1 is accessed, a T
t
state, in which only the
CSn
and address signals
are asserted, is inserted after the normal access cycle.
A one-state T
t
cycle is inserted regardless of 2-state or 3-state access designation, or the number of
program waits.
Bit n
CSXTn
Description
0
In area n basic bus interface access, the
CSn
and address assertion period (T
t
) is not
extended
(Initial value)
1
In area n basic bus interface access, the
CSn
and address assertion period (T
t
) is
extended
(n = 7 to 0)
Содержание H8S/2670
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