Hitachi H8S/2670, Справочное руководство

Страница: 76 / 647

59
3.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)
Bit 15 14 13 12 11 10 9 8
— IPR14 IPR13 IPR12 — IPR10 IPR9 IPR8
Initial value 0 1 1 1 0 1 1 1
Read/Write — R/W R/W R/W — R/W R/W R/W
Bit 7 6 5 4 3 2 1 0
— IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0
Initial value 0 1 1 1 0 1 1 1
Read/Write — R/W R/W R/W — R/W R/W R/W
The IPR registers are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 3.4.
The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'7777 by a reset and in hardware standby mode.
Bits 15, 11, 7, and 3—Reserved: These bits are always read as 0 and cannot be modified.
Table 3.4 Correspondence between Interrupt Sources and IPR Settings
Register Bits 14 to 12 Bits 10 to 8 Bits 6 to 4 Bits 2 to 0
IPRA IRQ0 IRQ1 IRQ2 IRQ3
IPRB IRQ4 IRQ5 IRQ6 IRQ7
IPRC IRQ8 IRQ9 IRQ10 IRQ11
IPRD IRQ12 IRQ13 IRQ14 IRQ15
IPRE DTC Interval timer —
*
Refresh timer
IPRF —
*
A/D converter TPU channel 0 TPU channel 1
IPRG TPU channel 2 TPU channel 3 TPU channel 4 TPU channel 5
IPRH 8-bit timer channel 0 8-bit timer channel 1 DMAC EXDMAC channel 0
IPRI EXDMAC channel 1 EXDMAC channel 2 EXDMAC channel 3 SCI channel 0
IPRJ SCI channel 1 SCI channel 2 —
*
—
*
IPRK —
*
—
*
—
*
—
*
Note: * Reserved bits. These bits are read as H'7, and the write value should be H'7.