302
RPOR2
*
R
P2nDDR
C
Q
D
Reset
WDDR2
R
P2nDR
C
Q
D
Reset
WDR2
System controller
EXPE
EXDMAC module
EDREQ
acknowledge
enable
EDREQ
acknowledge output
TPU module
Output compare output/
PWM output enable
Output compare output/
PWM output
Input capture input
PPG module
Pulse output enable
Pulse output
P2n
RDR2
Modes 1, 2, 4, 5, 6
Mode 7
Interrupt controller
ITSm
IRQm
Internal data bus
WDDR2: Write to P2DDR
WDR2:
Write to P2DR
RPOR2: Read port 2
RDR2: Read
P2DR
n = 6 or 7
m = 14 or 15
Note:
*
Output enable signal
Priority order: Modes 1, 2, 4, 5, 6, 7 (EXPE = 1)
EXDMAC
>
TPU
>
PPG
>
DR
Mode 7 (EXPE = 0)
TPU
>
PPG
>
DR
Figure 5.22 Port 2 Block Diagram (b) (Pins P26 and P27)
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