Hioki 3504-40 C HiTester, Инструкция по эксплуатации

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8.6 Things to Know before Beginning Communication
150
Standard Event Status Enable Register (SESER) ____________________
When the standard event status enable register is used to set each of the bits to
"1," the corresponding bits are enabled in the standard event status register.
Standard Event Status Register (SESR) and Standard Event Status Enable Reg-
ister (SESER)
Unique Event Status Registers (ESR0, ESR1, ESR2, ESR3) ___________
Four event status registers have been provided for managing events in the unit.
An event status register is an 8-bit register.
If even one of the event status register bits enabled by the event status enable
register becomes "1," the corresponding bit becomes as follows.
• When event status register 0: Bit 0 (ESB0) of the status byte register becomes
"1"
• When event status register 1: bit 1 (ESB1) becomes "1"
• When event status register 2: bit 2 (ESB2) becomes "1"
• When event status register 3: bit 3 (ESB3) becomes "1"
The content of event status register 0, 1, 2, and 3 is cleared at the following
times.
• The "
* CLS
" command is executed.
• An event status register query is executed
(
:
ESR0?,:ESR1?,:ESR2?,:ESR3?
)
• The power is turned on again.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PON URQ CME EXE DDE QYE RQC OPC
& & & & & & & &
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PON URQ CME EXE DDE QYE RQC OPC
Logical
OR
Standard Event Status Register (SESR)
Standard Event Status Enable Register (SESER)
bit6 bit5 bit4
SRQ
MSS
ESB MAV