APPENDIX
COPYRIGHT © 2001 CANON INC. CANON CLC1000/1000S/3100 REV.2 MAY 2001 PRINTED IN JAPAN (IMPRIME AU JAPON)
A-16
DC Controller Circuit Diagram (2/36)
G*
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
12
13
14
15
12
13
14
15
16
17
18
19
20
21
16
17
18
19
20
21
22
23
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
RESET*
CPUCLK
P
addoc
kEn*
MHWR*
ML
WR*
MRD*
DB
US<15.,0>
42
43
44
45
46
47
48
49
0
1
2
3
4
5
6
7
8
9
10
20
22
23
11
12
13
14
15
50
51
R
OMCS0*
52
PM51
PM5EO
VCC
PM5XE
PM5CK
GND
PM44
PM43
PM42
PM41
PM4EO
GND
VCC
PM4XE
PM4CK
TST1
TST0
PM34
PM33
PM32
PM31
PM3EO
PM3XE
PM3CK
GND
VCC
GND
PM24
PM23
PM22
PM21
PM2EO
PM2XE
PM2CK
GND
PM14
PM13
PM12
PM11
GND
VCC
PM1EO
PM1XE
PM1CK
GND
PM04
PM03
PM02
PM01
PM0EO
PM0XE
PM0CK
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
RvsMtrPls4
RvsMtrPls3
RvsMtrPls2
RvsMtrPls1
RvsMtrEn
CP2266
RvsMtrClk
PreFixMtrPls4
PreFixMtrPls3
PreFixMtrPls2
PreFixMtrPls1
PreFixMtrClk
132
131
130
129
128
127
126
125
124
123
JgMtrPls4
JgMtrPls3
JgMtrPls2
JgMtrPls1
JgMtrEn
JgMtrEnIn
JgMtrClk
122
121
Y
odoMtrPls4
120
1
2
3
4
5
6
7
8
9
10
11
12
VIN8
V
OUT8
V
OUT7
VIN7
GND
RESET
VREF
DO
VIN6
V
OUT6
V
OUT5
VIN5
24
23
22
21
20
19
18
17
16
15
14
HvSubDcC
HvSubDcY
HvT
rnsC
HvT
rnsY
13
VIN1
V
OUT1
V
OUT2
VIN2
VDO
LD
CLK
DI
VIN3
V
OUT3
HvGr
idY
HvGr
idC
D
A0LD
D
A0CLK
D
A0D
A
T
A
HvDe
vDconY
HvDe
vDconC
V
OUT4
VIN4
119
118
117
116
115
Y
odoMtrEn
114
113
Y
odoMtrPls3
Y
odoMtrPls2
Y
odoMtrPls1
Y
odoMtrEnIn
Y
odoMtrClk
112
111
110
109
108
107
106
105
RegMtrPls4
RegMtrPls3
RegMtrPls2
RegMtrPls1
RegMtrEnIn
RegMtrClkIn
GND
AB
US<23.,0>
PA
1
PA
2
PA
3
PA
4
PA
5
PA
6
A12
A13
A14
A15
VCC
GND
A16
A17
A18
A19
A20
A21
A22
A23
GND
RSTN
GND
XIN
GND
EN
HWRN
L
WRN
RDN
GND
D0
D1
D2
D3
D4
D5
D6
D7
VCC
GND
D8
D9
D10
D11
D12
D13
D14
D15
GND
CS00N
CS01N
R
OMCS1*
EXTCS*
RGCS0*
RGCS1*
P
ADDOCK2*
RAMCS0*
IOCS0*
IOCS1*
IOCS2*
IOCS3*
IOCS4*
IOCS5*
IOCS6*
IOCS7*
IOCS8*
IPCCS*
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
TEST
CT4IN
CT4GT
GND
CT4OT
CT3GT
GND
CT3OT
CT3IN
CT2IN
CT2GT
GND
VCC
CT2OT
CT1OT
GND
CT1GT
CT1IN
CT0IN
CT0GT
GND
CT0OT
PM84
PM83
PM82
PM81
GND
VCC
PM8EO
PM8XE
PM8CK
GND
PM74
PM73
PM72
PM71
PM7EO
PM7XE
PM7CK
GND
VCC
PM64
PM63
PM62
PM61
PM6EO
PM6XE
PM6CK
GND
PM54
PM53
PM52
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
OhpSens
OhpSensOut
FsrMtrOL
FsrMtrErr
JgMtrClk
JgMtrEn
JgMtrCntOut
Y odoMtrCntOut
Y odoMtrEn
Y odoMtrClk
RegMtrCntClk
RegMtrCntGate
RegMtrEnOut
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
CS10N
CS11N
CS12N
CS13N
CS14N
CS15N
CS16N
CS02N
CS20N
CS21N
CS22N
VCC
GND
CS23N
CS24N
CS25N
CS26N
CS27N
CS28N
CS29N
CS2AN
CS2BN
CS2CN
CS2DN
CS2EN
GND
CS2FN
DA0DT
DA0CK
DA0LD
DA1DT
DA1CK
DA1LD
DA2DT
DA2CK
DA2LD
DA3DT
DA3CK
DA3LD
DA0D
A TA
DA0CLK
DA0LD
DA1D
A TA
DA1CLK
DA1LD
DA2D
A TA
DA2CLK
DA2LD
DA3D
A TA
DA3CLK
DA3LD
VCC
GND
CK00T
CK10T
CK20T
CK30T
CK40T
CK50T
CK60T
CK70T
RegMtrCntClk
Y odoMtrClk
JgMtrClk
PreFixMtrClk
RvsMtrClk
T rnsBltMtrClk
FsrMtrClk
BfMtr1Clk
CK80T
CK90T
CLK152
GND
Q2323
+5V
RGV1
RGV6
RGV6
RGV6
+5V
RGV1
+5V
LS240
14
6
1
Q2458
LS240
12
8
1
Q2458
Q2279
(RST* - RESET*)
HC240
11
13
15
17
Y
odoMtrCntOut
JgMtrCntOut
RST*
RESET
19
9
7
5
3
Y
odoMtrEnIn
JgMtrEnIn
RESET
RESET*
A4
A3
A2
A1
Y4
Y3
Y2
Y1
Q2481
HC138
3
2
1
4
6
5
7
9
10
11
C
AB
US<23.,0>
B
A
Y7
Y6
Y5
Y4
12
13
14
15
21
19
Y3
Y2
Y1
Y0
G2A
G2B
G1
Q2306
1
CS01*
2
3
HC06
Q2315
DA
0
C2349
C2344
C2347
1
2
3
4
5
6
7
8
9
10
11
12
VIN8
V
OUT8
V
OUT7
VIN7
GND
RESET
VREF
DO
VIN6
V
OUT6
V
OUT5
VIN5
24
23
22
21
20
19
18
17
16
15
14
13
VIN1
V
OUT1
V
OUT2
VIN2
VDO
LD
CLK
DI
VIN3
V
OUT3
HvSpr
tDc
HvPreFsrDc
D
A2LD
D
A2CLK
D
A2D
A
T
A
HvInElmDc
V
OUT4
VIN4
RGV1
+5V
RGV1
Q2313
DA
2
C2350
1
2
3
4
5
6
7
8
9
10
11
12
VIN8
V
OUT8
V
OUT7
VIN7
GND
RESET
VREF
DO
VIN6
V
OUT6
V
OUT5
VIN5
24
23
22
21
20
19
18
17
16
15
14
HvSubDcK
HvSubDcM
HvT
rnsK
HvT
rnsM
13
VIN1
V
OUT1
V
OUT2
VIN2
VDO
LD
CLK
DI
VIN3
V
OUT3
HvGr
idM
HvGr
idK
D
A1LD
D
A1CLK
D
A1D
A
T
A
HvDe
vDconM
HvDe
vDconK
V
OUT4
VIN4
RGV1
+5V
RGV1
Q2316
DA
1
C2348
Q2299
1
2
3
D
A30LD
HC32
D
A3LD
Q2277
2
3
CS01*
ML
WR*
1
HC02
Q2306
4
5
6
HC06
RESET*
+5V
+5V
+5V
+5V
15
Q2278
5
6
3
1
ECLK
D
A3LD
2
J
K
PR
HC112
CLR
Q
Q*
CK
4
Q2299
4
5
6
D
A31LD
HC32
D
A3LD
Q2277
5
6
P
ADDOCK2*
ML
WR*
4
HC02
+5V
14
Q2278
9
7
11
13
CPUCLKA
12
J
K
PR
HC112
CLR
Q
Q*
CK
10
+5V
1
Q2302
5
6
2
3
D
PR
HC74
CLR
Q
Q*
CK
4
+5V
13
Q2302
9
8
12
11
D
PR
HC74
CLR
Q
Q*
CK
10
P
ADDOCK
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Страница 840: ...0501GR PRINTED IN JAPAN IMPRIME AU JAPON This publication is printed on 100 reprocessed paper...