ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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DPWM Zero Order Hold Division Register (DPWM_ZOHDIV)
Register
Offset
R/W Description
Reset Value
DPWM_ZOHDIV
0x10
R/W DPWM Zero Order Hold Division Register
0x0000_0804
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
CLKDIV
15
14
13
12
11
10
9
8
CLKDIV
7
6
5
4
3
2
1
0
ZOHDIV
Bits
Description
[31:19]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[18:8]
CLKDIV
Clock Divider
Divider to generate the DPWM_CLK
F_DPWM_CLK = (F_DPWM_CLK_SRC) / (1 + CLKDIV)
where F_ DPWM _CLK_SRC is the frequency of DPWM module clock source, which is
defined in the clock control register DPWMSEL (CLK_CLKSEL2[13:12]) and F_DPWM_CLK
is the frequency of DPWM module working clock (DPWM_CLK).
Note 1:
If fs is 48 kHz, the frequency of DPWM_CLK must be 24.576 MHz or 24 MHz
according to the value of CLKSET (DPWM_CTL[31]).
Note 2:
If fs is 96 kHz, the frequency of DPWM_CLK must be 49.152 MHz or 48 MHz
according to the value of CLKSET (DPWM_CTL[31]).
[7:0]
ZOHDIV
Zero Order Hold, Down-sampling Divisor
The input sample rate of the DPWM is set by DPWM_CLK frequency and the divisor set in
this register by the following formula:
If CLKSET (DPWM_CTL[31]) is 0, K = 128.
If CLKSET (DPWM_CTL[31]) is 1, K = 125.
ZOHDIV = F_DPWM_CLK / (Fs * K ).
Where F_DPWM_CLK is the frequency of DPWM module working clock (DPWM_CLK) and
Fs is sampling rate.
Note:
The value of ZOHDIV must be >= 4
