ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
163
of 928
Rev1.09
IS
D
9
410
0
S
ER
IE
S
T
E
C
HN
ICA
L
RE
F
E
RE
NCE
M
AN
U
AL
Clock Divider Number Register 0
(CLK_CLKDIV0)
Register
Offset
R/W Description
Reset Value
CLK_CLKDIV0
0x20
R/W Clock Divider Number Register 0
0x0006_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
EADCDIV
15
14
13
12
11
10
9
8
Reserved
UART0DIV
7
6
5
4
3
2
1
0
USBDIV
HCLKDIV
Bits
Description
[31:24]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[23:16]
EADCDIV
EADC Clock Divide Number From EADC Clock Source
EADC clock frequency = (EADC clock source frequency) / (E 1).
[15:12]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[11:8]
UART0DIV
UART0 Clock Divide Number From UART0 Clock Source
UART0 clock frequency = (UART0 clock source frequency) / (UA 1).
[7:4]
USBDIV
USB Clock Divide Number From PLL Clock
USB clock frequency = (USB clock source frequency) / ( 1).
[3:0]
HCLKDIV
HCLK Clock Divide Number From HCLK Clock Source
HCLK clock frequency = (HCLK clock source frequency) / (H 1).
