ISD94100 Series Technical Reference Manual
Sep 9, 2019
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ADC Interrupt Source Enable Control Registers (EADC_INTSRC0~EADC_INTSRC3)
Register
Offset
R/W Description
Reset Value
EADC_INTSRC0
0xD0
R/W ADC interrupt 0 Source Enable Control Register.
0x0000_0000
EADC_INTSRC1
0xD4
R/W ADC interrupt 1 Source Enable Control Register.
0x0000_0000
EADC_INTSRC2
0xD8
R/W ADC interrupt 2 Source Enable Control Register.
0x0000_0000
EADC_INTSRC3
0xDC
R/W ADC interrupt 3 Source Enable Control Register.
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
SPLIE12
SPLIE11
SPLIE10
SPLIE9
SPLIE8
7
6
5
4
3
2
1
0
SPLIE7
SPLIE6
SPLIE5
SPLIE4
SPLIE3
SPLIE2
SPLIE1
SPLIE0
Bits
Description
[31:13]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[12]
SPLIE12
Sample Module 12 Interrupt Enable Bit
0 = Sample Module 12 interrupt Disabled.
1 = Sample Module 12 interrupt Enabled.
[11]
SPLIE11
Sample Module 11 Interrupt Enable Bit
0 = Sample Module 11 interrupt Disabled.
1 = Sample Module 11 interrupt Enabled.
[10]
SPLIE10
Sample Module 10 Interrupt Enable Bit
0 = Sample Module 10 interrupt Disabled.
1 = Sample Module 10 interrupt Enabled.
[9]
SPLIE9
Sample Module 9 Interrupt Enable Bit
0 = Sample Module 9 interrupt Disabled.
1 = Sample Module 9 interrupt Enabled.
[8]
SPLIE8
Sample Module 8 Interrupt Enable Bit
0 = Sample Module 8 interrupt Disabled.
1 = Sample Module 8 interrupt Enabled.
[7]
SPLIE7
Sample Module 7 Interrupt Enable Bit
0 = Sample Module 7 interrupt Disabled.
1 = Sample Module 7 interrupt Enabled.