ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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is listed in Table 6.6.5-1.
PDMA_PRISET
Channel Number
Priority Setting
Arbitration Priority In Descending Order
1
15
Channel15, Fixed Priority
Highest
1
14
Channel14, Fixed Priority
---
---
---
---
---
1
0
Channel0, Fixed Priority
---
0
15
Channel15, Round-Robin Priority
---
0
14
Channel14, Round-Robin Priority
---
---
---
---
---
0
0
Channel0, Round-Robin Priority
Lowest
Table 6.6.5-1 Channel Priority Table
6.6.5.2
PDMA Operation Mode
The PDMA controller supports two operation modes including Basic mode and Scatter-Gather
mode.
Basic Mode
Basic mode is used to perform one descriptor table transfer mode. This mode can be used to
transfer data between memory and memory or peripherals and memory. PDMA controller operation
mode can be set from OPMODE (PDMA_DSCTn_CTL[1:0], n denotes PDMA channel), default
setting is in idle state (OPMODE (PDMA_DSCTn_CTL[1:0]) = 0x0) and recommend user configure
the descriptor table in idle state. If operation mode is not in idle state, user re-configure channel
setting may make some operation error.
User must fill the transfer count TXCNT (PDMA_DSCTn_CTL[31:16]) register and select transfer
width TXWIDTH (PDMA_DSCTn_CTL[13:12]), destination address increment size DAINC
(PDMA_DSCTn_CTL[11:10]), source address increment size SAINC (PDMA_DSCTn_CTL[9:8]),
burst size BURSIZE (PDMA_DSCTn_CTL[6:4]) and transfer type TXTYPE
(PDMA_DSCTn_CTL[2]), then the PDMA controller will perform transfer operation in transfer state
after receiving request signal. Finishing this task will generate an interrupt to CPU if corresponding
PDMA interrupt bit INTENn (PDMA_INTEN[15:0]) is enabled and the operation mode will be
updated to idle state as shown in Figure 6.6-3. If software configures the operation mode to idle
state, the PDMA controller will not perform any transfer and then clear this operation request.
Finishing this task will also generate an interrupt to CPU if corresponding PDMA interrupt bit is
enabled.