ISD94100 Series Technical Reference Manual
Sep 9, 2019
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6.15.7 Register Description
CRC Control Register
(CRC_CTL)
Register
Offset
R/W Description
Reset Value
CRC_CTL
0x00
R/W CRC Control Register
0x2000_0000
31
30
29
28
27
26
25
24
CRCMODE
DATLEN
CHKSFMT
DATFMT
CHKSREV
DATREV
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
CHKSINIT
CRCEN
Bits
Description
[31:30]
CRCMODE
CRC Polynomial Mode
This field indicates the CRC operation polynomial mode.
00 = CRC-CCITT Polynomial mode.
01 = CRC-8 Polynomial mode.
10 = CRC-16 Polynomial mode.
11 = CRC-32 Polynomial mode.
[29:28]
DATLEN
CPU Write Data Length
This field indicates the write data length.
00 = Data length is 8-bit mode.
01 = Data length is 16-bit mode.
1x = Data length is 32-bit mode.
Note:
When the write data length is 8-bit mode, the valid data in CRC_DAT register is only
DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register
is only DATA[15:0].
[27]
CHKSFMT
Checksum 1’s Complement
This bit is used to enable the 1’s complement function for checksum result in
CRC_CHECKSUM register.
0 = 1’s complement for CRC checksum Disabled.
1 = 1’s complement for CRC checksum Enabled.
[26]
DATFMT
Write Data 1’s Complement
This bit is used to enable the 1’s complement function for write data value in CRC_DAT
register.
0 = 1’s complement for CRC writes data in Disabled.
1 = 1’s complement for CRC writes data in Enabled.