ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
166
of 928
Rev1.09
IS
D
9
410
0
S
ER
IE
S
T
E
C
HN
ICA
L
RE
F
E
RE
NCE
M
AN
U
AL
PLL Control Register
(CLK_PLLCTL)
Register
Offset
R/W Description
Reset Value
CLK_PLLCTL
0x40
R/W PLL Control Register
0x0005_8430
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
STBSEL
Reserved
PLLSRC
OE
BP
PD
15
14
13
12
11
10
9
8
OUTDIV
INDIV
FBDIV
7
6
5
4
3
2
1
0
FBDIV
Bits
Description
[31:24]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[23]
STBSEL
PLL Stable Counter Selection (Write Protected)
0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less
than 12 MHz).
1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12
MHz).
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[22:20]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[19]
PLLSRC
PLL Source Clock Selection (Write Protected)
0 = PLL source clock from external high-speed crystal oscillator (HXT).
1 = PLL source clock from internal high-speed oscillator (HIRC).
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[18]
OE
PLL OE (FOUT Enable) Pin Control (Write Protected)
0 = PLL FOUT Enabled.
1 = PLL FOUT is fixed low.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[17]
BP
PLL Bypass Control (Write Protected)
0 = PLL is in normal mode (default).
1 = PLL clock output is same as PLL input clock FIN.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[16]
PD
Power-down Mode (Write Protected)
If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode,
too.
