ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Clock Status Monitor Register
(CLK_STATUS)
The bits in this register are used to monitor if the chip clock source is stable or not, and whether the
clock switch is failed.
Register
Offset
R/W Description
Reset Value
CLK_STATUS
0x50
R
Clock Status Monitor Register
0x0000_0018
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
CLKSFAIL
Reserved
HIRCSTB
Reserved
PLLSTB
LXTSTB
HXTSTB
Bits
Description
[31:8]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[7]
CLKSFAIL
Clock Switching Fail Flag (Read Only)
This bit is updated when software switches system clock source (CLK_CLKSEL0[2:0]). If
switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this
bit will be set to 1.
0 = Clock switching success.
1 = Clock switching failure.
[6:5]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[4]
HIRCSTB
HIRC Clock Source Stable Flag (Read Only)
0 = Internal high speed RC oscillator (HIRC) clock is not stable or disabled.
1 = Internal high speed RC oscillator (HIRC) clock is stable and enabled.
[3]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[2]
PLLSTB
Internal PLL Clock Source Stable Flag (Read Only)
0 = Internal PLL clock is not stable or disabled.
1 = Internal PLL clock is stable and enabled.
[1]
LXTSTB
LXT Clock Source Stable Flag (Read Only)
0 = External low speed crystal oscillator (LXT) clock is not stable or disabled.
1 = External low speed crystal oscillator (LXT) clock is stabled and enabled.
[0]
HXTSTB
HXT Clock Source Stable Flag (Read Only)
