ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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System Control Register (SCR)
Register
Offset
R/W Description
Reset Value
SCR
0xD10
R/W System Control Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
SEVONPEND
Reserved
SLEEPDEEP SLEEPONEXIT
Reserved
Bits
Description
[31:5]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[4]
SEVONPEND
Send Event on Pending
0 = Only enabled interrupts or events can wake up the processor, while disabled interrupts
are excluded.
1 = Enabled events and all interrupts, including disabled interrupts, can wake up the
processor.
When an event or interrupt enters pending state, the event signal wakes up the processor
from WFE. If the processor is not waiting for an event, the event is registered and affects
the next WFE.
The processor also wakes up on execution of an SEV instruction or an external event.
[3]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[2]
SLEEPDEEP
Processor Deep Sleep and Sleep Mode Selection
Control Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode.
0 = Sleep.
1 = Deep sleep.
[1]
SLEEPONEXIT
Sleep-on-exit Enable Control
This bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.
0 = Do not sleep when returning to Thread mode.
1 = Enters sleep, or deep sleep, on return from an ISR to Thread mode.
Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty
main application.
[0]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
