ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
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Rev1.09
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ICA
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NCE
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SPI Slave Select Control Register (SPI0_SSCTL)
Register
Offset
R/W Description
Reset Value
SPI0_SSCTL
0x08
R/W SPI0 Slave Select Control Register
0x0000_0000
31
30
29
28
27
26
25
24
SLVTOCNT
23
22
21
20
19
18
17
16
SLVTOCNT
15
14
13
12
11
10
9
8
Reserved
SSINAIEN
SSACTIEN
Reserved
SLVURIEN
SLVBEIEN
7
6
5
4
3
2
1
0
Reserved
SLVTORST
SLVTOIEN
SLV3WIRE
AUTOSS
SSACTPOL
SS1
SS
Bits
Description
[31:16]
SLVTOCNT
Slave Mode Time-out Period (Only Supported in SPI0)
In Slave mode, these bits indicate the time-out period when there is bus clock input during
slave select active. The clock source of the time-out counter is Slave peripheral clock. If the
value is 0, it indicates the slave mode time-out function is disabled.
[15:14]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[13]
SSINAIEN
Slave Select Inactive Interrupt Enable Bit
0 = Slave select inactive interrupt Disabled.
1 = Slave select inactive interrupt Enabled.
[12]
SSACTIEN
Slave Select Active Interrupt Enable Bit
0 = Slave select active interrupt Disabled.
1 = Slave select active interrupt Enabled.
[11:10]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[9]
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit
0 = Slave mode TX under run interrupt Disabled.
1 = Slave mode TX under run interrupt Enabled.
[8]
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit
0 = Slave mode bit count error interrupt Disabled.
1 = Slave mode bit count error interrupt Enabled.
[7]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[6]
SLVTORST
Slave Mode Time-out Reset Control (Only Supported in SPI0)
0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by
hardware.