ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
259
of 928
Rev1.09
IS
D
9
410
0
S
ER
IE
S
T
E
C
HN
ICA
L
RE
F
E
RE
NCE
M
AN
U
AL
Port A-D High Slew Rate Control Register (Px_SLEWCTL)
Register
Offset
R/W Description
Reset Value
PA_SLEWCTL
0x028
R/W PA High Slew Rate Control Register
0x0000_0000
PB_SLEWCTL
0x068
R/W PB High Slew Rate Control Register
0x0000_0000
PC_SLEWCTL
0x0A8
R/W PC High Slew Rate Control Register
0x0000_0000
PD_SLEWCTL
0x0E8
R/W PD High Slew Rate Control Register
0x0000_0000
31
30
29
28
27
26
25
24
HSREN15
HSREN14
HSREN13
HSREN12
23
22
21
20
19
18
17
16
HSREN11
HSREN10
HSREN9
HSREN8
15
14
13
12
11
10
9
8
HSREN07
HSREN6
HSREN5
HSREN4
7
6
5
4
3
2
1
0
HSREN03
HSREN2
HSREN1
HSREN0
Bits
Description
[2n+1:2n]
n=0,1..15
HSRENn
Port A-D Pin[n] High Slew Rate Control
00 = Px.n output with normal slew rate mode.
01 = Px.n output with high slew rate mode.
10 = Px.n output with fast slew rate mode.
11 = Reserved. Do not use.
Note:
Max. n=15 for port A/C/D
n=0..9, 13, 14, 15 for port B