Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Interrupt and Trap Functions
5 - 11 Micronas
The table below shows a few examples of each action executed with each particular
programming of an interrupt control register.
Note: All requests on levels 13 … 1 cannot initiate PEC transfers. They are always
serviced by an interrupt service routine. No PECC register is associated and no
COUNT field is checked.
Interrupt Control Functions in the PSW
The Processor Status Word (PSW) is functionally divided into 2 parts: the lower byte of
the PSW basically represents the arithmetic status of the CPU, the upper byte of the
PSW controls the interrupt system of M2 and the arbitration mechanism for the external
bus interface.
Note: Pipeline effects have to be considered when enabling/disabling interrupt requests
via modifications of register PSW.
Priority Level Type of Service
ILVL GLVL COUNT = 00
H
COUNT

00
H
1 1 1 1 1 1 CPU interrupt,
level 15, group priority 3 PEC service,
channel 7
1 1 1 1 1 0 CPU interrupt,
level 15, group priority 2 PEC service,
channel 6
1 1 1 0 1 0 CPU interrupt,
level 14, group priority 2 PEC service,
channel 2
1 1 0 1 1 0 CPU interrupt,
level 13, group priority 2 CPU interrupt,
level 13, group priority 2
0 0 0 1 1 1 CPU interrupt,
level 1, group priority 3 CPU interrupt,
level 1, group priority 3
0 0 0 1 0 0 CPU interrupt,
level 1, group priority 0 CPU interrupt,
level 1, group priority 0
0 0 0 0 X X No service! No service!