Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
System Control & Configuration
6 - 4 Micronas
6.1 System Reset
The internal system reset function provides the initialization of the M2 into a defined
default state and is invoked either by asserting a hardware reset signal on pin RSTIN
(Hardware Reset Input), upon the execution of the SRST instruction (Software Reset) or
by an overflow of the watchdog timer.
Whenever one of these conditions occurs, the CBC is reset into its predefined default
state through an internal reset procedure. When a reset, other than a watchdog reset, is
initiated, pending internal hold states are cancelled and any external bus cycle is aborted
(see description).
After the reset condition is removed, M2 will start program execution from memory
location 00’0000
H
in code segment zero. This start location will typically hold a branch
instruction to the start of a software initialization routine for the configuration of
peripherals and M2 SFRs.
M2 recognizes the following reset conditions.
Reset conditions are indicated in the WDTCON register.
Hardware Reset
A hardware reset is triggered asynchronously by a falling edge of the reset input signal,
RSTIN. To ensure the recognition of the RSTIN signal, it must be held low for at least
2 CPU clock cycles, assuming the clock input signal is stable. Also, shorter RSTIN
pulses may trigger a hardware reset, however, this is not recommended. The internal
reset condition is prolonged until one of the following conditions arises:
• the rising edge of the RSTIN signal, or
• the termination of the reset sequence, if RSTIN was deasserted before, or
• the termination of the lengthening conditions.
After termination of the reset state, program execution will start.
Three different kinds of hardware reset conditions are considered:
• Power-on Reset
A complete power-on reset requires an active RSTIN time until a stable clock signal
is available. The on-chip oscillator needs about 2 ms to stabilize.
Reset Type Short-cut Condition
Power-on Reset PONR Power-on
Short Hardware Reset SHWR 16 TCL <
t
RSTIN

2048 TCL
Long Hardware Reset LHWR
t
RSTIN
> 2048 TCL
Watchdog Timer Reset WDTR WDT overflow
Software Reset SWR SRST command