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Micronas SDA 6000, User Manual

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SDA 6000

PRELIMINARY DATA SHEET

Version 2.1

System Control & Configuration

6 - 20

Micronas

 

6.7

Watchdog Timer

The watchdog timer is a 16-bit up counter which can be clocked with the CPU clock
(

f

CPU

), either divided by 2 or divided by 128. This 16-bit timer is realized as two

concatenated 8-bit timers (see 

Figure 6-3

). The upper 8 bits of the watchdog timer can

be preset to a user-programmable value via a watchdog service access in order to vary
the watchdog expire time. The lower 8 bits are reset on each service access.

The following figure shows the WDT block diagram:

Figure 6-3

WDT Block Diagram

The current count value of the Watchdog Timer is contained in the Watchdog Timer
Register WDT, which is a non-bitaddressable read-only register. The operation of the
Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register
WDTCON. This register specifies the reload value for the high byte of the timer and
selects the input clock prescaling factor.

After any software reset, external hardware reset (see note), or watchdog timer reset,
the watchdog timer is enabled and starts counting up from 0000

H

 with the frequency

f

CPU

/2. The input frequency may be switched to 

f

CPU

/128 by setting bit WDTIN. The

watchdog timer can be disabled via the instruction DISWDT (Disable Watchdog Timer).
Instruction DISWDT is a protected 32-bit instruction which will ONLY be executed during
the time between a reset and execution of either the EINIT (End of Initialization) or the
SRVWDT (Service Watchdog Timer) instruction. Either one of these instructions
disables the execution of DISWDT.

When the watchdog timer is not disabled via instruction DISWDT it will continue counting
up, even during Idle Mode. If it is not serviced by the SRVWDT instruction by the time
the count reaches FFFF

H

 the watchdog timer will overflow and cause an internal reset.

In this case the Watchdog Timer Reset Indication Flag (WDTR) in register WDTCON will
be set.

UEB11133

WDT Control

WDT Low Byte

WDT

f

MUX

WDTIN

DISWDT

Clear

WDT High Byte

WDTREL

WDTR

2

÷

128

÷

Summary of Contents for SDA 6000

Page 1: ...USER S MANUAL SDA 6000 Teletext Decoder with Embedded 16 bit Controller Edition March 1 2001 6251 557 1...

Page 2: ...ives worldwide see our webpage at http www micronas com SDA 6000 Revision History Current Version 2000 06 15 Previous Version 08 99 Page Subjects major changes since last revision Complete Update of C...

Page 3: ...Contents Overview...

Page 4: ...Bus Interface EBI 4 13 4 5 1 Memory Mapping 4 16 4 5 2 Register Description 4 19 4 5 3 Crossing Memory Boundaries 4 23 4 6 Central Processing Unit 4 24 4 6 1 Instruction Pipelining 4 26 4 6 2 Bit Hand...

Page 5: ...1 1 1 Timer Concatenation 7 14 7 1 2 Functional Description of Timer Block 2 7 19 7 1 2 1 Core Timer T6 7 20 7 1 2 2 Auxiliary Timer T5 7 21 7 1 2 3 Timer Concatenation 7 22 7 1 3 GPT Registers 7 26 7...

Page 6: ...Overview 7 100 7 5 2 The Physical I2 C Bus Interface 7 100 7 5 3 Functional Overview 7 103 7 5 4 Registers 7 105 7 6 Analog Digital Converter 7 118 7 6 1 Power Down and Wake Up 7 119 7 6 2 Register De...

Page 7: ...ze of Transferred Memory Area TDR 10 42 10 7 12 Offset of Transferred Memory Area TOR 10 43 10 7 13 Attributes of Transfer TAR 10 44 11 D A Converter 11 3 11 1 Register Description 11 3 12 Slicer and...

Page 8: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 A 7 Micronas 14 1 Absolute Maximum Ratings 14 3 14 2 Operating Range 14 3 14 3 DC Characteristics 14 4 14 4 Timings 14 10 14 5 Package Outlines 14 11...

Page 9: ...Levels and PEC Channels 5 10 Figure 5 2 Mapping of PEC Offset Pointers into the Internal RAM 5 19 Figure 5 3 Task Status Saved on the System Stack 5 22 Figure 5 4 Pipeline Diagram for Interrupt Respo...

Page 10: ...ous Mode of Serial Channel ASC0 7 57 Figure 7 31 ASC0 Synchronous Mode Waveforms 7 59 Figure 7 32 ASC0 Baud Rate Generator Circuitry in Asynchronous Modes 7 61 Figure 7 33 ASC0 Baud Rate Generator Cir...

Page 11: ...ernally Generated Flash Signals in Different Flash Phases 10 16 Figure 10 14 16 bit Pixel Format 5 6 5 for Use in Frame Buffer 10 16 Figure 10 15 Overview of GA 10 17 Figure 10 16 Use of Register Sett...

Page 12: ...w within M2 Chapter 4 C16X Microcontroller Gives a detailed explanation of the 16 bit C architecture Chapter 5 Interrupt and Trap Functions Explains the powerful C166 Interrupt facilities Chapter 6 Sy...

Page 13: ...standing of this specification it is recommended to read the documentation listed in the following table Moreover it gives an overview of the software drivers which are available for M2 Document Name...

Page 14: ...generation of M2 is based on frame buffer technology A frame buffer concept displays information which is individually stored for each pixel allowing greater flexibility with screen menus Proportiona...

Page 15: ...f the software and displayed information MATE stands for M2 Advanced Tool Environment Using MATE two primary goals are achieved shorter Time to Market and improved SW qualitiy In detail Re usability T...

Page 16: ...ed System M2 RTOS PC Simulator EVA Board C166 Available Debugging UEB11114 Object Library Manager info M2 formatted data Converter Display data Object Code C Compiler New Tool Generation Simulator Use...

Page 17: ...te data and control code for the M2 graphical user interface GDI without having knowledge of M2 hardware These are Display Generator Simulator Teletext Data Slicer Simulator GDI Graphical Device Inter...

Page 18: ...m External SDRAM Embedded Refresh Controller for External SDRAM Enhanced Programmable Low Power Modes Single 6 MHz Crystal Oscillator Multinorm H V Display Synchronization in Master or Slave Mode Free...

Page 19: ...0 MHz to 50 MHz Up to 65536 Displayable Colors in one Frame DMA Functionality Graphic Accelerator Functions Draw Lines Draw and Fill Rectangle etc 1 2 4 or 8 bit Bitmaps up to 256 out of 4096 colors 1...

Page 20: ...Figure 1 2 Logic Symbol UEL11115 SS V DD 3 3 V V XTAL1 Address 16 Bit XTAL2 RSTIN CVBS1A CVBS1B CVBS2 R G B COR BLANK HSYNC VSYNC RD WR CSROM CSSDRAM MEMCLK UDQM LDQM CLKEN 16 Bit Data Port 2 8 Bit 1...

Page 21: ...Pin Description...

Page 22: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Pin Descriptions 2 3 Micronas 2 Pin Descriptions...

Page 23: ...5 33 63 53 43 VSS33 3 V SS33 6 VDDA 4 85 TCK TDI TDO P2 8 P2 9 P2 10 P2 11 P2 12 P2 13 P2 14 P2 15 V SS33 1 DD33 1 V P4 5 CS3 P4 4 A20 P4 3 A19 P4 2 A18 P4 1 A17 SS25 1 V DD25 1 V P4 0 A16 A8 A7 A6 A5...

Page 24: ...RAM address bit 26 A6 R6 C6 O Address bit SDRAM address bit 24 A7 R7 C7 O Address bit SDRAM address bit 23 A8 R8 O Address bit SDRAM address bit 25 A9 R9 O Address bit SDRAM address bit 28 A10 R10 O A...

Page 25: ...t port Address bit 18 P4 2 A18 O General purpose output port Address bit 17 P4 3 A19 O General purpose output port Address bit 16 P4 4 A20 O General purpose output port Address bit 15 P4 5 CS3 O Gener...

Page 26: ...EX5IN I O General purpose I O port External interrupt 5 11 P2 14 EX6IN I O General purpose I O port External interrupt 6 12 P2 15 EX7IN I O General purpose I O port External interrupt 7 74 P3 0 SCL0...

Page 27: ...or A D converter 127 P5 3 AN 3 I General purpose I O port Analog input for A D converter 93 P5 14 T4EUD I O General purpose I O port GPT1 timer T4 ext up down ctrl input 94 P5 15 T2EUD I O General pur...

Page 28: ...2 5 V 115 118 122 VSSA2 4 S Analog ground 116 119 123 VDDA2 4 S Analog power for ADCs 2 5 V 20 86 VSS25 1 2 S Digital ground for digital core 21 87 VDD25 1 2 S Digital power for digital core 2 5 V 13...

Page 29: ...Architectural Overview...

Page 30: ...2 T3 T4 GPT2 T5 T6 2 C RTC Watchdog OCDS JTAG Port 5 Port 3 Port 2 Port 4 6 15 8 8 D Sync 3 3 x 6 Bit DAC FIFO SRU GA XRAM Interrupt Controller PEC 36 nodes 8 ext OSC 6 MHz Internal RAM 2 Kbyte 16 16...

Page 31: ...definition instead of the former character orientated attribute definition For the processing of this new pixel based attribute definition the display generator architecture is divided in two subblock...

Page 32: ...ts normally used as a TTX slicer Slicer 2 requests used as a WSS slicer Graphic accelerator requests Screen refresh unit requests Data requests from the CPU via XBUS Instruction requests via the CPU p...

Page 33: ...C16X Microcontroller...

Page 34: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 C16X Microcontroller 4 3 Micronas 4 C16X Microcontroller...

Page 35: ...he display generator unpredictable wait states for the controller may occur These wait states do not destroy the overall average system performance because they are mostly buffered by the CPU related...

Page 36: ...by the External PEC which allows an external device to trigger a PEC transfer while providing the source and destination pointers New features also include the packet transfer mode and the channel lin...

Page 37: ...m allows the detection of specific events during user program execution through software and hardware breakpoints An additional communication module allows communication between the OCDS and an extern...

Page 38: ...ates via 2 busses with the memory interface In normal operation mode access to segments 00H to 41H excluding internal memory areas is mapped to the read only program memory bus PMBUS whereas access to...

Page 39: ...address being followed by the high byte at the next odd byte address Double words instructions only are stored in ascending memory locations as two subsequent words Single bits are always stored in t...

Page 40: ...oller 4 9 Micronas Figure 4 2 Storage of Words Byte and Bits in a Byte Organized Memory Note Byte units forming a single word or a double word must always be stored within the same physical internal e...

Page 41: ...ose Register Banks GPRs Source and Destination Pointers for the Peripheral Event Controller PEC Variable and other data storage or Code storage Figure 4 3 Internal RAM Areas and SFR Areas Note The upp...

Page 42: ...are provided for single bit storage and thus they are bit addressable 4 3 1 System Stack The system stack may be defined within the IRAM The size of the system stack is controlled by bit field STKSZ...

Page 43: ...s a base address independent of the current DPP register contents In addition each bit in the currently active register bank can be accessed individually M2 supports fast register bank context switchi...

Page 44: ...7 0 In M2 these pointers are used to specify the address offset within the segment and the destination source segment numbers are specified in designated SFRs see Chapter 5 2 Figure 4 4 Location of t...

Page 45: ...ctive control status bits can directly be modified or checked using bit addressing When accessing registers in the ESFR area using 8 bit addresses or direct bit addressing an Extend Register EXTR inst...

Page 46: ...T Version 2 1 C16X Microcontroller 4 15 Micronas Note The tools are equipped to monitor accesses to the ESFR area and will automatically insert EXTR instructions or issue a warning in case of missing...

Page 47: ...device which can be used for frame buffers character sets pixel graphics acquisitions microcontroller workspace and any other data storage purposes Using a 100 MHz external memory bus the theoretical...

Page 48: ...n 2 1 C16X Microcontroller 4 17 Micronas memory size is limited by the number of external address lines Up to 21 external address lines are configurable thus devices providing up to 4 MByte of static...

Page 49: ...figuration of different external SDRAM types can be controlled by a special SW driver as well as refresh modes and power down features The microcontroller and the acquisition unit use a common interfa...

Page 50: ...ions are in different SDRAM banks Detailed timings and the specification of setup and hold conditions can be found in Chapter 14 Figure 4 6 Interlocked Access Cycles to ROM and SDRAM ROM_Adr RD CSROM...

Page 51: ...sses unless otherwise noted Figure 4 8 gives a coarse depiction without redirection of the mapping process in normal operation mode UET11120 MEMCLK Pre Act Act Pre Act Read Read Read Read RAS CAS SDRA...

Page 52: ...r not addressable at all C To get access to these segments use REDIR1 a Internal mapping of the C16x Access to segments 0 to 64 selects the PMBUS The address range 00 0000H 40 FFFFH is mapped to the r...

Page 53: ...ped to 80 0000H address REDIR_LOWER 16 kBytes 3 If the total amount of static memeory in 4 MBytes or less i e SALSEL 111 or SALSEL 111 and no second device present and the address resulting from step...

Page 54: ...ions for executing operations in direct mode 4 5 2 Register Description Access cycles to addresses specified by bit fields REDIR_LOWER and REDIR_UPPER are redirected by hardware to the SDRAM area The...

Page 55: ...ent part of the address is replaced by REDIR1_SEG Bit Function EDMR EBI Direct Mode Request Flag 0 EBI direct mode is disabled 1 EBI direct mode is enabled Note This bit is only used for EBI direct mo...

Page 56: ...d EDMA bit is still valid This phase will only take one EBI clock period no EDMA polling required Phase IV EBI is waiting for the next direct mode request When executing a direct mode command the EBI...

Page 57: ...les the user has to provide the EBI with information about the external memory configuration and memory sizes The combination of reset configuration and the SDRSZE bit of the EBICON register includes...

Page 58: ...y sized blocks of different granularity and into logical memory areas Crossing the boundaries between these Bit Function CSENA Chip Select Enable 0 CS3 is active for 2nd ROM device 1 CS3 is inactive S...

Page 59: ...d via the code segment pointer CSP for code fetches and via an explicit segment number for data accesses overriding the standard DPP scheme During code fetching segments are not changed automatically...

Page 60: ...rd and exceptional timing For instruction and operand fetches the CPU is connected to the different areas external memory program memory internal dual port RAM or E SFR area either internally or throu...

Page 61: ...on chip Peripheral Event Controller PEC System errors detected during program execution so called hardware traps are also processed as standard interrupts with a very high priority Besides its normal...

Page 62: ...In this stage all external operands and the remaining operands within the internal RAM space are written back A particularity of the CPU are the so called imported instructions These imported instruc...

Page 63: ...lly required to fetch the branch target instruction This extra machine cycle is provided by means of an imported instruction see Figure 4 12 Figure 4 12 Standard Branch Instruction Pipelining If a con...

Page 64: ...mory but taken from the cache and immediately imported into the decoding stage of the pipeline see Figure 4 13 A time saving jump on cache is always taken after the second and any further occurrence o...

Page 65: ...tes a physical operand address via a particular DPPn n 0 to 3 register is mostly not capable of using a new DPPn register value which is to be updated by an immediately preceding instruction Thus to m...

Page 66: ...ts Note The described delay of 1 instruction also applies for enabling the interrupts system i e no interrupt requests are acknowledged until the instruction after the enabling instruction Changing th...

Page 67: ...ear or set the specified bit when the jump is taken The instructions JB and JNB also conditional jump instructions that refer to flags evaluate the specified bit to determine if the jump is to be take...

Page 68: ...hine cycle which is also the general minimum execution time This section summarizes the execution times in a very condensed way A detailed description of the execution times for the various instructio...

Page 69: ...s in the CPU core is identical to the access mechanism for any other SFR Since all SFRs can simply be controlled by means of any instruction which is capable of addressing the SFR memory space a lot o...

Page 70: ...ation Control 0 Latched select line mode for X Peripherals 1 Select lines for access cycles via XBUS are directly derived from the address lines Note CSCFG 1 is recommended The effect of the switch is...

Page 71: ...the CSP register is pushed onto the system stack in addition to the IP register before an interrupt service routine is entered and it is repopped when the interrupt service routine is left again Syst...

Page 72: ...PSW register after execution of the immediately preceding instruction Note After reset all of the ALU status bits are cleared Bit Function N Negative Result Set when the result of an ALU operation is...

Page 73: ...ese operations cannot cause a carry For shift and rotate operations the C flag represents the value of the bit last shifted out If a shift count of zero is specified the C flag will be cleared The C f...

Page 74: ...ed by those instructions which cannot be reasonably used for table search operations In all other cases the E flag is set depending on the value of the source operand to signify whether the end of a s...

Page 75: ...r to Chapter 5 After reset all interrupts are globally disabled and the lowest priority ILVL 0 is assigned to the initial CPU activity The Instruction Pointer IP This register determines the 16 bit in...

Page 76: ...mode the content of this register is not significant because all code accesses are automatically restricted to segment 0 Note The CSP register can only be read but not written by data operations It i...

Page 77: ...g active simultaneously at run time The lower 10 bits of each DPP register select one of the 1024 possible 16 Kbyte data pages while the upper 6 bits are reserved for future use The DPP registers allo...

Page 78: ...pecify one of the 1024 possible data pages This data page base address together with the 14 bit page offset forms the physical 24 bit address selectable part is driven to the address pins In case of n...

Page 79: ...PR within the current register bank of up to 16 word and or byte GPRs CP ResetValue FC00H Bit Function cp Modifiable Portion of Register CP Specifies the word base address of the current register bank...

Page 80: ...CP register can be updated via any instruction which is capable of modifying an SFR Note Due to the internal instruction pipeline a new CP value is not yet usable for GPR address calculations of the...

Page 81: ...thin a range from F0H to FFH interpret the four least significant bits as short 4 bit GPR addresses while the four most significant bits are ignored The respective physical GPR address calculation is...

Page 82: ...register If the contents of the SP register are less than the content of the STKOV register a stack overflow hardware trap will occur Since the least significant bit of register STKOV is tied to 0 an...

Page 83: ...nd after each addition to the SP register If the content of the SP register is greater than the content of the STKUN register a stack underflow hardware trap will occur Since the least significant bit...

Page 84: ...16 bit remainder MDH ResetValue 0000H Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 When multip...

Page 85: ...ired control information for the corresponding multiply or divide operations The MDC register is updated by hardware during each single cycle of a multiply or divide instruction MDC ResetValue 0000H W...

Page 86: ...ter addressable constant of all zeros i e for bit manipulation or mask generation It can be accessed via any instruction which is capable of addressing an SFR ZEROS Reset Value 0000H The Constant Ones...

Page 87: ...vision Code Identifies the device step where the first release is marked 01H CHIPID 7 0 Device Identification Identifies the device name Bit Function MANUF JEDEC Normalized Manufacturer Code 0C1H Infi...

Page 88: ...Interrupt and Trap Function...

Page 89: ...ggered by an interrupt request the PEC performs a single word or byte data transfer between any two locations in the whole memory space through one of nine programmable PEC Service Channels During a P...

Page 90: ...erand field of the instruction which is a seven bit trap number The reserved vector locations build a jump table in the low end of the address space segment 0 The jump table is made up of the appropri...

Page 91: ...FF62H 00 008CH 23H 35D GPT1 Timer 4 T4IC 00 FF64H 00 0090H 24H 36D GPT2 Timer 5 T5IC 00 FF66H 00 0094H 25H 37D GPT2 Timer 6 T6IC 00 FF68H 00 0098H 26H 38D GPT2 CAPREL Register CRIC 00 FF6AH 00 009CH 2...

Page 92: ...d therefore have the highest priority trap priority IV Software traps may be initiated to any vector location between 00 0000H and 00 01FCH A service routine entered via a software TRAP instruction is...

Page 93: ...serviced if its priority is higher than the current CPU priority in the PSW register Table 5 2 Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap Priority Reset Functions Hard...

Page 94: ...register are reserved All interrupt control registers are bit addressable and all bits can be read or written via software This allows each interrupt source to be programmed or modified with just one...

Page 95: ...increases with the numerical value of ILVL so 0000B is the lowest and 1111B is the highest priority level When more than one interrupt request on a specific level becomes active at the same time the...

Page 96: ...at are programmed to priority levels 13 through 1 will always be serviced by normal interrupt processing Note Priority level 0000B is the default level of the CPU Therefore a request on level 0 will n...

Page 97: ...controls the interrupt system of M2 and the arbitration mechanism for the external bus interface Note Pipeline effects have to be considered when enabling disabling interrupt requests via modification...

Page 98: ...i e 15 so no interrupt or PEC requests will be acknowledged while an exception trap service routine is being executed Note The TRAP instruction does not change the CPU level so software invoked trap s...

Page 99: ...uests that have already entered the pipeline at that time will be processed When IEN is set to 1 all interrupt sources which have been individually enabled by the interrupt enable bits in their associ...

Page 100: ...PEC functions are defined as follows Source pointer and destination pointer are extended to 24 bit pointer thus enabling PEC controlled data transfers between any two locations within the total addre...

Page 101: ...T at the time the request is activated selects the action COUNT may allow a specified number of PEC transfers unlimited transfers or no PEC service at all The table below summarizes how the COUNT fiel...

Page 102: ...ecuted if their priority level is higher than the CPU level i e only PEC channels 7 4 are processed while the CPU executes on level 14 All interrupt request sources that are enabled and programmed for...

Page 103: ...nnels If linking is not enabled the CLT bit of both channels is always zero The internal channel link flag CLT toggles and the other channel begins servicing with the next request if the old channel s...

Page 104: ...ISNC ResetValue 0000H The source and destination pointers specifiy the locations between which the data is to be moved PEC transfers can be performed between any locations in the entire memory space o...

Page 105: ...gment Number address bits A23 16 used for addressing the source of the respective PEC transfer PECDSN 7 0 PEC Destination Segment Number 8 bit Segment Number address bits A23 16 used for addressing th...

Page 106: ...and the global enable bit must both be set The Priority Level automatically selects a certain group of interrupt requests that will be acknowledged disclosing all other requests The priority level of...

Page 107: ...of this class will be accepted The example below establishes 3 interrupt classes which cover 2 or 3 interrupt priorities depending on the number of members in a class A level 6 interrupt disables all...

Page 108: ...abled The CPU priority field ILVL in PSW is updated with the priority of the interrupt request that is to be serviced so the CPU now executes on the new level If multiplication or division was in prog...

Page 109: ...utine may now use its own registers This register bank is preserved when the service routine terminates i e its contents are available on the next call Before returning RETI the previous CP is simply...

Page 110: ...is 6 state times 12 TCL The interrupt response time is increased by all delays of the instructions in the pipeline that are executed before entering the service routine including N When internal hold...

Page 111: ...interrupt response time is the time needed to perform 3 word bus accesses When the interrupt vector of the example above is pointing into the internal code memory the interrupt response time is 1 word...

Page 112: ...um PEC response time is 3 states 6 TCL This requires program execution from the internal code memory no external operand read requests and setting the interrupt request flag during the last state of a...

Page 113: ...e PEC response time is the time needed to perform 7 word bus accesses When instructions N and N 1 are executed out of the external memory but all operands for instructions N 3 through N 1 are in inter...

Page 114: ...ery 2 TCL The interrupt request arbitration and processing however is executed every 8 TCL In Sleep mode no clock is available for sampling but interrupt request detection is still possible on fast in...

Page 115: ...ion The interrupt service routine called by a TRAP instruction must be terminated with a RETI return from interrupt instruction to ensure correct operation Note The CPU level in register PSW is not mo...

Page 116: ...OCDS is set apart and has its own individual priority and vector address The bit addressable Trap Flag Register TFR allows a trap service routine to identify the kind of trap which caused the exceptio...

Page 117: ...ponding flags in the TFR register are set and the trap service routine is entered Since all class B traps have the same vector the priority of service of simultaneously occurring class B traps is dete...

Page 118: ...enever the stack pointer is decremented to a value which is less than the value in the stack overflow register STKOV the STKOF flag in the TFR register is set and the CPU will enter the stack overflow...

Page 119: ...e opcode the PRTFLT flag in register TFR is set and the CPU enters the protection fault trap routine The protected instructions include DISWDT EINIT IDLE PWRDN SRST and SRVWDT The IP value pushed onto...

Page 120: ...rrupts may also have interrupt sources selected from other peripherals This function is very advantageous in Slow Down or in Sleep mode if for example the A D converter input shall be used to wakeup t...

Page 121: ...ult pin 0 1 Input from alternate source 1 0 Input from default pin ORed with alternate source 1 1 Input from default pin ANDed with alternate source Fast Interrupt Alternate Source input FEIxIN_B 0 AD...

Page 122: ...System Control Configuration...

Page 123: ...anagement It is implemented to ease compatibility of new M2 based products with already existing C16x derivatives M2 provides the following functions for system control and configuration System and Co...

Page 124: ...owing reset conditions Reset conditions are indicated in the WDTCON register Hardware Reset A hardware reset is triggered asynchronously by a falling edge of the reset input signal RSTIN To ensure the...

Page 125: ...can be triggered at any time via the protected instruction SRST Software Reset This instruction can be executed deliberately within a program e g to leave bootstrap loader mode or upon a hardware tra...

Page 126: ...400H set according to start up configuration BUSCON0 15B7H set according to start up configuration ONES FFFFH fixed value 6 1 3 The Internal RAM after Reset The contents of the internal RAM are not af...

Page 127: ...e selections as shown below Registers SYSCON and BUSCON0 are initialized according to the selected configuration Pins that control the operation of the internal control logic and reserved pins are eva...

Page 128: ...he selection which pins of Port 4 drive address lines and which are used for general purpose I O The three bits are latched in register RP0H Depending on the system architecture the required address s...

Page 129: ...nagement they need to be accessed during operation to select the appropriate mode The switching between the different security levels is controlled by a state machine By using a password and command s...

Page 130: ...a read only register which shows the current password the actual security level and the state of the switching state machine The SCUSLS is defined as follows Bit Function Command Code of Command to be...

Page 131: ...nprotected Write Mode 01 Low Protected Mode 10 Reserved 11 Write Protected Mode STATE Current State 000 State 0 Wait for Command 0 001 State 1 Wait for Command 1 010 State 2 Wait for Command 2 011 Sta...

Page 132: ...to the associated addresses will influence the state machine for security level switching Write Access in Low Protected Mode The write access in low protected mode is also done via a command sequence...

Page 133: ...dic wake up from idle mode The periodic wake up combines the reduced power consumption in power reduction modes with a high level of system availability External signals and events can be scanned at a...

Page 134: ...xecuted the CPU continues executing the program with the instruction following the IDLE instruction Otherwise if the interrupt request cannot be serviced because of a too low priority or a globally di...

Page 135: ...e accessed The watchdog timer may be used to monitor the Idle mode an internal reset will be generated if no interrupt request occurs before the watchdog timer overflows To prevent the watchdog timer...

Page 136: ...ing reset otherwise the output pins of Port 4 represent the port latch data During Power Down mode the oscillator and the clocks to the CPU and peripherals are turned off Like in idle mode all port pi...

Page 137: ...16 bit word are written The oscillator input XTAL1 and output XTAL2 connect the internal oscillator to the external crystal The oscillator provides an inverter and a feedback element An external TTL...

Page 138: ...S1B or single ended CVBS1A CVBS1B to ground R G B are analog outputs from the display generator CORBLA is a signal which indicates whether a pixel created by M2 should be displayed or mixed with exter...

Page 139: ...dary some registers have to be set to guarantee correct operation The user has to program the XBUS registers in the following way Register Value SYSCON E444H XADRS1 0E03H XADRS2 0E83H XADRS3 XADRS6 no...

Page 140: ...he timer and selects the input clock prescaling factor After any software reset external hardware reset see note or watchdog timer reset the watchdog timer is enabled and starts counting up from 0000H...

Page 141: ...ctions the Protection Fault Trap will be entered rather than the instruction being executed The time period for an overflow of the watchdog timer is programmable in two ways The input frequency of the...

Page 142: ...WDT Reset Value 0000H Note This register in a read only register Write access can be performed to this register during test mode only Bit Function WDTIN Watchdog Timer Input Frequency Selection 0 Inpu...

Page 143: ...te When the reset output is enabled the indicated flags are also set in the respective reset case The WDTCON reset value will then be different from the table value Note The listed reset values for WD...

Page 144: ...level loader routine Figure 6 4 Bootstrap Loader Sequence The M2 enters BSL mode if pin P4 0 is sampled low at the end of a hardware reset When M2 has entered BSL mode the following configuration is...

Page 145: ...is disabled therefore the bootstrap loading sequence is not time limited Pin TXD0 is configured as output The configuration e g the accessibility of the M2 s memory areas after reset in Bootstrap Loa...

Page 146: ...n and revision code IDMEM for identification of on chip program memory type size IDMEM2 for identification of additional EEPROM OTP DRAM or Flash memory IDPROG for identification of programming erasin...

Page 147: ...DEC normalized manufacturer code 0C1H Infineon Technologies 020H SGS Thomson DEPT Department Indicates the department within Micronas and Infineon Technologies 00H HL MC 01H HL CAD Macrocells 02H HL I...

Page 148: ...terms of 4 K blocks i e Memory size Size 4 KByte Type Type of On chip Program Memory Identifies the memory type on this silicon 0H ROMless 1H Mask ROM 2H EPROM 3H Flash 4H OTP 5H EEPROM 6H DRAM SRAM B...

Page 149: ...on RIX Redesign Index 0 This device is the original Revision else This device has experienced minor changes that are not reflected to the customer by the Revision bit field RA Redundancy Activation 0...

Page 150: ...have programmable alternate input or output functions associated with them GPT1 GPT2 external interrupts I2 C bus analog inputs for A D converter SSC interface or ASC interface All port lines that ar...

Page 151: ...bit y Bit Function DP2 y Port direction register DP2 bit y DP2 y 0 Port line P2 y is an input high impedance DP2 y 1 Port line P2 y is an output 5 4 3 2 1 0 11 10 9 8 7 6 15 14 13 12 rw rw rw rw rw r...

Page 152: ...0000H Bit Function P3 y Port data register P3 bit y Bit Function DP3 y Port direction register DP3 bit y DP3 y 0 Port line P3 y is an input high impedance DP3 y 1 Port line P3 y is an output 5 4 3 2...

Page 153: ...ead at runtime from register RP0H For a detailed description refer to Chapter 6 1 Bit Function ODP3 y Port 3 Open Drain control register bit y ODP3 y 0 Port line P3 y output driver in push pull mode O...

Page 154: ...pose output If segment address lines are selected the alternate function of Port 4 may be necessary to access e g external memory directly after reset For this reason Port 4 will be automatically swit...

Page 155: ...15 and 5 14 also serve as external timer control lines for GPT1 and GPT2 Port 4 Pin Altern Function SALSEL 111 Altern Function SALSEL 110 Altern Function SALSEL 101 Altern Function SALSEL 100 Altern F...

Page 156: ...H Port 5 Pin Alternate Function P5 0 P5 1 P5 2 P5 3 P5 14 P5 15 ANA0Analog Input 0 Wake Up Function ANA1Analog Input 1 ANA2Analog Input 2 ANA3 Analog Input 3 T4EUDTimer 4 External Up Down Input T2EUDT...

Page 157: ...trol register bit y ODP6 y 0 Port line P6 y output driver in push pull mode ODP6 y 1 Port line P6 y output driver in open drain mode Port 6 Pin Alternate Function P6 0 P6 1 P6 2 P6 3 P6 4 P6 5 P6 6 TR...

Page 158: ...Value 0000H Bit Function SELP6 y Alternate Function Control Bit SELP6 y 0 General Purpose Port Functionality enabled for Line P6 y SELP6 y 1 Alternate Function enabled for Line P6 y 5 4 3 2 1 0 11 10...

Page 159: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 System Control Configuration 6 40 Micronas...

Page 160: ...Peripherals...

Page 161: ...rsion 2 1 Peripherals 7 3 Micronas 7 Peripherals All of the peripherals described in the following paragraphs are clocked with the same clock as the CPU fhw_clk Depending on the mode normal or Idle th...

Page 162: ...T1 The following enumeration summarizes all features to be supported Timer Block 1 fhw_clk 4 maximum resolution 3 independent timers counters Timers counters can be concatenated 4 operating modes tim...

Page 163: ...d or capture is to be performed the CPU write operation has priority in order to guarantee correct results Figure 7 1 Structure of Timer Block 1 Core Timer T3 The operation of the core timer T3 is con...

Page 164: ...ng up With a high level T3EUD the timer is counting down If T3UD 1 a high level at line T3EUD specifies counting up and a low level specifies counting down The count direction can be changed regardles...

Page 165: ...d BPS1 The input frequency fT3 for timer T3 and its resolution rT3 are scaled linearly with lower module clock frequencies as can be seen from the following formula Table 7 2 gives an overview for tim...

Page 166: ...same options are available for the input frequency as for the timer mode However the input clock to the timer in this mode is gated by the external input line T3IN Timer T3 External Input an associate...

Page 167: ...o 001B In counter mode timer T3 is clocked by a transition at the external input line T3IN The event causing an increment or decrement of the timer can be a positive a negative or both a positive and...

Page 168: ...ocked by each transition on one or both of the external input lines which gives 2 fold or 4 fold the resolution of the encoder input Figure 7 5 Block Diagram of Core Timer T3 in Incremental Interface...

Page 169: ...The third encoder output T0 which indicates the mechanical zero position may be connected to an external interrupt input and trigger a reset of timer T3 Figure 7 6 Interfacing the Encoder to the Micr...

Page 170: ...Table 7 5 summarizes the possible combinations The figures below give examples of T3 s operation visualizing count signal generation and direction control It also shows how input jitter is compensate...

Page 171: ...ted with the core timer or they may be used as reload or capture registers in conjunction with the core timer The individual configuration for the T2 and T4 timers is determined by their bit addressab...

Page 172: ...T4 in Counter Mode In counter mode timers T2 and T4 can be clocked either by a transition at the respective external input line TxIN or by a transition of timer T3 s output toggle latch T3OTL Figure 7...

Page 173: ...If both positive and negative transitions of T3OTL are used to clock the auxiliary timer this timer is clocked on every overflow underflow of the core timer T3 Thus the two timers form a 32 bit timer...

Page 174: ...f two different signals The trigger signal is selected the same way as the clock source for counter mode see Table 7 6 i e a transition of the auxiliary timer s input or the output toggle latch T3OTL...

Page 175: ...will be reloaded with the contents of the auxiliary timer each time it overflows or underflows This is the standard reload mode reload on overflow underflow If either a positive or a negative transit...

Page 176: ...if required to modify the PWM signal However this will NOT trigger the reloading of T3 Note An associated port pin linked to line T3OUT should be configured as output Figure 7 12 GPT1 Timer Reload Con...

Page 177: ...ificant bit TxI 2 is irrelevant for capture mode It is recommended to keep this bit cleared TxI 2 0 Note When programmed for capture mode the respective auxiliary timer T2 or T4 stops independent of i...

Page 178: ...catenation of T6 with auxiliary timer T5 while concatenation of T6 with other timers is provided through line T6OFL Triggered by an external signal the contents of T5 can be captured in register CAPRE...

Page 179: ...T5 Therefore the lines and bits are named Tx Timer 6 Overflow Underflow Monitoring An overflow or underflow of timer T6 will clock the toggle latch T6OTL in control register T6CON T6OTL can also be se...

Page 180: ...andled by the associated Run Control Bit T5R in register T5CON Alternatively a remote control option T5RC is set may be enabled to start and stop T5 via the run bit T6R of core timer T6 Note The auxil...

Page 181: ...er T6OTL 16 bit auxiliary timer The count directions of the two concatenated timers are not required to be the same This offers a wide variety of different configurations In this case T6 can operate i...

Page 182: ...ration from the input signals When a selected transition at the external input line CAPIN is detected the contents of the auxiliary timer T5 are latched into register CAPREL and interrupt request flag...

Page 183: ...CAPREL is loaded into timer T6 This will not set the interrupt request flag CRIR associated with the CAPREL register However interrupt request flag T6IR will be set indicating the overflow underflow...

Page 184: ...eared T5CLR 1 Thus register CAPREL always contains the correct time between two operations measured in timer T5 increments Timer T6 which runs in timer mode counting down with a frequency of e g fhw_c...

Page 185: ...n described is eliminated in the example T5 would capture 63H 99D and the output frequency would be 80 KHz The underflow signal of timer T6 can furthermore be used to clock one or more of the CAPCOM u...

Page 186: ...ace mode see Table 7 11 for encoding T3M 5 3 rw Timer 3 Mode Control 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 100 Reserved Do not use...

Page 187: ...2 3 4 is fhw_clk 8 01 For Timer 2 3 4 is fhw_clk 4 10 For Timer 2 3 4 is fhw_clk 32 11 For Timer 2 3 4 is fhw_clk 16 T3EDGE 13 rwh Timer 3 Edge Detection The bit is set on each successful edge detecti...

Page 188: ...put Parameter Selection for Counter Mode T3I Triggering Edge for Counter Update 000 None Counter T3 is disabled 001 Positive transition raising edge on T3IN 010 Negative transition falling edge on T3I...

Page 189: ...terface mode see Table 7 14 for encoding TxM 5 3 rw Timer x Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high...

Page 190: ...for TxCHDIR and TxEDGE interrupts in Incremental Interface Mode is disabled TxEDGE 13 rwh Timer x Edge Detection The bit is set on each successful edge detection The bit has to be reset by SW 0 No cou...

Page 191: ...one Counter Tx is disabled 0 0 1 Positive transition raising edge on TxIN 0 1 0 Negative transition falling edge on TxIN 0 1 1 Any transition raising or falling edge on TxIN 1 0 1 Positive transition...

Page 192: ...bination 1XX Reserved Do not use this combination T6R 6 rw Timer 6 Run Bit 0 Timer Counter 6 stops 1 Timer Counter 6 runs T6UD 7 rw Timer 6 Up Down Control 0 Counting Up 1 Counting Down T6OTL 10 rwh T...

Page 193: ...fhw_clk BPS2 11 000 4 2 16 8 001 8 4 32 16 010 16 8 64 32 011 32 16 128 64 100 64 32 256 128 101 128 64 512 256 110 256 128 1024 512 111 512 256 2048 1024 Table 7 16 Timer 6 Input Parameter Selection...

Page 194: ...e 010 Reserved Do not use this combination 011 Reserved Do not use this combination 1XX Reserved Do not use this combination T5R 6 rw Timer 5 Run Bit 0 Timer Counter 5 stops 1 Timer Counter 5 runs T5U...

Page 195: ...4 rw Timer 5 Clear Bit 0 Timer 5 is not cleared on a capture operation 1 Timer 5 is cleared on a capture operation T5SC 15 rw Timer 5 Capture Mode Enable 0 Capture into register CAPREL disabled 1 Capt...

Page 196: ...Sources Interrupt Interrupt Node Description Timer 2 Overflow T2IC Interrupt is requested on overflow of timer 2 if counting up Timer 2 Underflow T2IC Interrupt is requested on underflow of timer 2 i...

Page 197: ...tal Interface Mode T4I 110 Edge Detection Timer 4 T4IC Interrupt is requested on a successful detected edge resulting in a timer count action T4I 111 Reload Action Timer 2 T2IC Interrupt is requested...

Page 198: ...ing and for flexible interrupt generation and three counter registers that contain the actual time and date The interrupts are programmed via one interrupt subnode register and via an interrupt node r...

Page 199: ...of the CPU clock frequency without loading the general purpose timers or to wake up regularly from idle mode The T14 overflow interrupt RTC_T14INT cycle time can be adjusted via the timer T14 reload r...

Page 200: ...nd request flag its own enable and request flag located in register RTCISNC After an RTC interrupt RTC_INT is arbitrated the interrupt service routine has to check all the enabled sources request flag...

Page 201: ...er T14 generates the input clock for the RTC register and the periodic interrupt Bit Function TIMERREL14 15 0 16 Bit Reload Register for Timer 14 Represents the 16 bit reload value for T14 Bit Functio...

Page 202: ...f 32 Bit Capture Register RTCH2 5 0 Bit Function RTCRELL1 5 0 Low Word of 32 Bit Reload Register RTCRELL0 9 0 Bit Function RTCRELH2 5 0 High Word of 32 Bit Reload Register RTCRELH3 9 0 5 4 3 2 1 0 11...

Page 203: ...Overflow Interrupt Enable Control Bit 0 Interrupt request is disabled 1 Interrupt request is enabled RTCxIR RTCx Interrupt Request Flag 0 No request pending 1 This source has raised an interrupt reque...

Page 204: ...Function RTCINTIR RTC Interrupt Request Flag 0 No request pending 1 RTC has raised an interrupt request RTCINTIE RTC Interrupt Enable Control Bit 0 Interrupt request is disabled 1 Interrupt request i...

Page 205: ...nous operating modes Detection of standard baud rates 1200 2400 4800 9600 19200 38400 57600 115200 230400 Baud Detection of non standard baud rates Detection of asynchronous modes 7 bit even parity 7...

Page 206: ...s Serial Port Control Baud Rate Timer Prescaler Fractional Divider Detection Autobaud DIV f Coding IrDA MUX Decoding IrDA MUX TxD RxD 33 MHz 2 3 or Serial Port Control Buffers and Shift Registers Rece...

Page 207: ...ter S0TBUF by way of an instruction or a PEC data transfer Only the number of data bits which is determined by the selected operating mode will actually be transmitted e g bits written to positions 9...

Page 208: ...ived character in the receive buffer is overwritten The Loop Back option selected by bit S0LB allows the data currently being transmitted to be received simultaneously in the receive buffer This may b...

Page 209: ...der MUX S0FDE S0BRS S0R 33 MHz Serial Port Control Shift Clock Shift Clock S0REN S0FEN S0OEN S0PEN S0LB S0RIR S0EIR S0TIR S0TBIR Receive Int Request Transmit Int Request Transmit Buffer Int Request Er...

Page 210: ...us 8 Bit Frames 9 Bit Data Frames 9 bit data frames either consist of 9 data bits D8 D0 S0M 100B of 8 data bits D7 D0 plus an automatically generated parity bit S0M 111B or of 8 data bits D7 D0 plus w...

Page 211: ...p bit cleared The slaves that were not being addressed remain in 8 bit data wake up bit mode ignoring the following data bytes IrDA Frames The modulation schemes of IrDA is based on standard asynchron...

Page 212: ...it data loaded into S0TBUF is immediately moved to the transmit shift register thus freeing S0TBUF for the next data to be sent This is indicated by the transmit buffer interrupt request line S0TBIR b...

Page 213: ...r the next start bit 1 to 0 transition at the receive data input pin The receiver input pin RXD0 must be configured for input Asynchronous reception is stopped by clearing bit S0REN A currently receiv...

Page 214: ...e width SxPWM bit 7 0 must be loaded with a value which assures that t IPW t IPW min RXD TXD Data Path Selection in Asynchronous Modes The data paths for the serial input and output data in asynchrono...

Page 215: ...use an IrDA coded receiver input signal for autobaud detection 7 3 2 Synchronous Operation Synchronous mode supports half duplex communication basically for simple I O expansion via shift registers Da...

Page 216: ...e transmit data loaded into S0TBUF is immediately moved to the transmit shift register thus freeing S0TBUF for the next data to be sent This is indicated by the transmit buffer interrupt request line...

Page 217: ...ut in order to support the shift clock Pin RXD0 must be configured as an alternate data input Synchronous reception is terminated by clearing bit S0REN A currently received byte is completed including...

Page 218: ...with the value stored in its 13 bit reload register each time it underflows The resulting clock fBRT is again divided according to the operating mode and controlled by the baud rate selection bit S0B...

Page 219: ...d Rates in Asynchronous Mode For asynchronous operation the baud rate generator provides a clock fBRT with 16 times the rate of the established baud rate Every received bit is sampled at the 7th 8th a...

Page 220: ...e content of the reload register S0BG taken as an unsigned 13 bit integer The maximum baud rate that can be achieved by the asynchronous modes when using the two fixed clock dividers and a CPU clock o...

Page 221: ...raction of n 512 for any value of n from 0 to 511 If n 0 the divider ratio is 1 which means that fDIV 33 33 MHz S0BG represents the content of the reload register S0BG taken as an unsigned 13 bit inte...

Page 222: ...ved in synchronous mode when using a CPU clock of 33 33 MHz is 4 166 MBaud 7 3 4 Autobaud Detection The autobaud detection unit provides an ability to recognize the mode and the baud rate of an asynch...

Page 223: ...tes to be detected standard or non standard baud rates Programming of the Prescaler Fractional Divider to select a specific value of fDIV Starting the Prescaler Fractional Divider setting CON_R Prepar...

Page 224: ...1 a 61H 0 8 Bit Even Parity Start 1 Start a 61 0 0 1 0 H 1 1 Parity Stop 1 0 0 1 Start 0 0 Start Parity Stop 1 0 1 1 Stop Start 0 0 0 1 1 1 H t 74 UED11154 Parity Stop 0 1 1 H 1 0 t 74 1 1 Parity Stop...

Page 225: ...art 1 Start A 41 0 0 0 0 H 1 1 Parity Stop 1 0 1 1 Start 0 0 Start Parity Stop 1 0 0 1 Stop Start 0 0 0 1 0 1 H T 54 UED11155 Parity Stop 0 0 1 H 1 0 T 54 1 0 Parity Stop 1 0 1 Stop A 41 0 8 Bit No Pa...

Page 226: ...U while the baud rate timer register BG is automatically initialized with a 13 bit value BR_VALUE after a successfull autobaud detection For the subsequent calculations the fractional divider is used...

Page 227: ...he value FD_VALUE in register FDV the fractional divider fDIV is adapted to the system clock frequency 33 MHz Table 7 21 defines the deviation of the standard baud rates when using autobaud detection...

Page 228: ...for this example 7 3 4 3 Overwriting Registers on Successful Autobaud Detection With a successful autobaud detection some bits in register CON and BG are automatically set to a value which corresponds...

Page 229: ...e only If the parity error detection enable bit S0PEN is set in the mode where a parity bit is received and the parity check on the received data bits proves false the parity error flag S0PE is set in...

Page 230: ...RIR is activated when the received frame is moved to S0RBUF While the task of the receive interrupt handler is quite clear the transmitter is serviced by two interrupt handlers This has its advantages...

Page 231: ...mitted 7 3 7 Register Description The operating mode of the serial channel ASC0 is controlled by its control register S0CON This register contains control bits for mode and error check selection and s...

Page 232: ...ud detection operation STP 3 rw 0 1 Number of Stop Bit Selection One stop bit Two stop bits REN 4 rwh 0 1 Receiver Enable Control Receiver disabled Receiver enabled Bit can be affected during autobaud...

Page 233: ...s don t care ODD 12 rwh 0 1 Parity Selection Even parity selected parity bit set on odd number of 1 s in data Odd parity selected parity bit set on even number of 1 s in data Bit is be set cleared by...

Page 234: ...y hardware after a successful autobaud detection with the stop bit detection of the second character Resetting ABEN by software if it was set aborts the autobaud detection AUREN 1 rw 0 1 Automatic Aut...

Page 235: ...interrupt ABDETIR becomes active after detection of the first and second byte of the two byte frame ABEM 8 9 rw 0 0 0 1 1 0 1 1 Autobaud Echo Mode Enable In echo mode the serial data at RXD is switche...

Page 236: ...ABCON_ABEN is set or if FCCDET or SCSDET or SCCDET is set Bit can be also cleared by software FCCDET 1 rwh 0 1 First Character with Capital Letter Detected no capital A character detected capital A c...

Page 237: ...econd Character with Capital Letter Detected no capital T character detected capital T character detected Bit is cleared by hardware when ABCON_ABEN is set or if FCSDET or FCCDET or SCSDET is set Bit...

Page 238: ...0 9 8 7 6 5 4 3 2 1 0 0 0 0 BR_VALUE Field Bits Type Value Description BR_VALUE 12 0 rw all Baud Rate Timer Reload Register Value Reading BG returns the 13 bit content of the baud rate timer bits 15 1...

Page 239: ...0 0 0 IRP W PW_VALUE Field Bits Type Value Description PW_VALUE 7 0 rw all IrDA Pulse Width Value PW_VALUE is the 8 bit value n which defines the variable pulse width of an IrDA pulse Depending on th...

Page 240: ...smission is double buffered therefore a new value can be written to TBUF before the transmission of the previous value is complete S0RBUF Transmitter Buffer Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 241: ...rate transmit error Three pin interface Flexible SSC0 pin configuration The High Speed Synchronous Serial Interface SSC0 provides serial communication between M2 and other microcontrollers microproces...

Page 242: ...ible with the popular SPI interface So it can be used to communicate with shift registers I O expansion peripherals e g EEPROMs etc or other controllers networking The SSC0 supports half duplex and fu...

Page 243: ...and takes place at the same time e g the same number of transmitted bits is also received Transmit data is written into the Transmit Buffer SSCTB It is moved to the shift register as soon as this is e...

Page 244: ...of frames of any data length from 2 bit characters up to 16 bit characters Starting with the LSB SSC0HB 0 allows communication e g with an SSC device in synchronous mode C166 family or 8051 like seri...

Page 245: ...it line which in turn is connected to the slaves shift register input The output of the slaves shift register is connected to the external receive line in order to enable the master to receive the dat...

Page 246: ...expects data either by separate select lines or by sending a special command to this slave The selected slave then switches its MRST line to output until it gets a deselection signal or command The s...

Page 247: ...ock pulses via the data width selection the data transmitted by the master is contained in all slaves shift registers while the master s shift register holds the data of the selected slave In the mast...

Page 248: ...e clock line is connected to the SCLK pin The master device controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and receive pi...

Page 249: ...es For example two byte transfers would look the same as one word transfer This feature can be used to interface with devices which can operate with or require more than 16 data bits per transfer How...

Page 250: ...slave select lines In this case it is not always necessary to switch the direction of a port pin 7 4 5 Baud Rate Generation The serial channel SSC0 has its own dedicated 16 bit baud rate generator wi...

Page 251: ...MHz 7 4 6 Error Detection Mechanisms The SSC0 is able to detect four different error conditions Receive Error and Phase Error are detected in all modes while Transmit Error and baud rate Error only ap...

Page 252: ...wo cycles after the latching edge of the shift clock signal SCLK This condition sets the error flag SSC0PE and when enabled via SSC0PEN the error interrupt request flag SSCEIR A Baud Rate Error Slave...

Page 253: ...he corruption of the data on the transmit receive line in half duplex mode open drain configuration if this slave is not selected for transmission This mode requires that slaves not selected for trans...

Page 254: ...st 1 Transmit Receive MSB First SSC0PH SSC0 Clock Phase Control Bit 0 Shift transmit data on the leading clock edge latch on trailing edge 1 Latch receive data on leading clock edge shift on trailing...

Page 255: ...ors 1 Check baud rate errors SSC0AREN SSC0 Automatic Reset Enable Bit 0 No additional action upon a baud rate error 1 The SSC is automatically reset upon a baud rate error SSC0MS SSC0 Master Select Bi...

Page 256: ...Do not write to SSC0TE SSC0 Transmit Error Flag 1 Transfer starts with the slave s transmit buffer not being updated SSC0RE SSC0 Receive Error Flag 1 Reception completed before the receive buffer was...

Page 257: ...data value Bit Function SSC0RL 15 0 Baud Rate Timer Reload Register Value Reading SSCBR returns the 16 bit content of the baud rate timer Writing SSC0BR loads the baud rate timer reload register Bit F...

Page 258: ...rals 7 100 Micronas SSCRB Reset Value 0000H Bit Function SSC0RD 7 0 Receive Data Register Value SSCRB contains the received data bits Unselected bits of SSC0RB will be not valid and should be ignored...

Page 259: ...the bus lines in slave mode Evaluation of the device address in slave mode Bus access arbitration in multimaster mode Features Extended buffer allows up to 4 send receive data bytes to be stored Suppo...

Page 260: ...condition and a stop condition 7 5 2 The Physical I2 C Bus Interface Communication via the I2 C Bus uses two bidirectional lines the serial data line SDA and the serial clock line SCL Each of these t...

Page 261: ...external system The channel can be dynamically switched by connecting the module to another pair of pins e g SDA1 and SCL1 This establishes physically separate interface channels Broadcasting Connecti...

Page 262: ...l pins of the M2 that are to be used for I2 C bus communication must be switched to output opendrain and their alternate function must be enabled by setting the respective port output latch to 1 befor...

Page 263: ...ddress in ICRTB0 an setting bit BUM at least one command nop has to be executed Operation in Multimaster Mode If multimaster mode is selected via bit field MOD in register ICCON the on chip I2 C modul...

Page 264: ...lected via bit ACKDIS For a reception the respective data byte is fetched from the buffer ICRTB0 3 after IRQD has been activated In both cases the data transfer itself is enabled by clearing bits IRQD...

Page 265: ...Buffer 00 E81AH 0000H IICPISEL2 2 Itus currently no function Should be left on reset value I2 C Port Input Select Register 00 E804H b 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRPL 0 0 SCL EN1 SCL...

Page 266: ...n multi master mode RSC cannot be set in slave mode Note RSC is cleared automatically after the repeated start condition has been sent MOD 3 2 rwh 00 01 10 11 Basic Operating Mode I2 C module is disab...

Page 267: ...transmitted to the I2 C bus Note TRX is set automatically when writing to the transmit buffer It is not allowed to delete this bit in the same buscycle It is automatically cleared after last byte as...

Page 268: ...WMEN 15 rwh 0 1 Write Mirror Enable write mirror is not active write mirror is active If RMEN is set WMEN can not be set and will remain zero If WMEN and RMEN are simultaneously set to 1 both will re...

Page 269: ...the bus but has lost the arbitration Operation is continued until the 9th clock pulse If multimaster mode is selected the I2 C module temporarily switches to slave mode after a lost arbitration Bit I...

Page 270: ...ledge bit of the last byte has been received or transmitted and is cleared automatically upon a complete read or write access to the buffer s ICRTB0 3 New data transfers will start immediately after c...

Page 271: ...bit must correspondingly be set by software IRQE 7 rwh 0 1 I2 C Interrupt Request Bit for Data Transmission End 1 No interrupt request pending A receive end event interrupt request is pending a stop i...

Page 272: ...C bus CO 10 8 rw 000 001 010 011 100 Counter of Transmitted Bytes Since Last Data Interrupt If a multi byte transmission could not be finished because of a missing acknowledge the number of correctly...

Page 273: ...in 7 bit mode ICA7 1 7 1 rw Node Address in 7 Bit Mode ICA9 and ICA0 disregarded ICA8 becomes IGE bit IGE 8 rw 0 1 Ignore IRQE In 7 bit mode this bit becomes IGE bit Ignore IRQE End of transmission in...

Page 274: ...rsions High baud rates may be configured precisely in mode 1 Mode 0 Reciprocal Divider The resulting baud rate is Mode 1 Fractional Divider The resulting baud rate is Table 7 24 I2 C Bus Baud Rate Sel...

Page 275: ...ved 2 If bit INT is set to zero and all bytes specified in CI of ICRTB0 3 are read written depending on bit TRX IRQD is cleared 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICRTB3 ICRTB2 15 14 13 12 11 10 9...

Page 276: ...he arbitration Protocol Slave Mode after Lost Arbitration I2 CPIC Interrupt is requested if multimaster mode is selected and the I2 C module temporarily switches to slave mode after a lost arbitration...

Page 277: ...t condition until receiving the next stop condition Change of transmit direction is possible only after a protocol interrupt IRQP or in initialization mode MOD 00B Initialization Before data can be se...

Page 278: ...A SHEET Version 2 1 Peripherals 7 120 Micronas bit field CO must be read in case the buffer size defined in CI is greater than one byte to decide which bytes in the receive buffer were received in the...

Page 279: ...The S H circuit is open for about 2 s New results are available in ADDAT1 and ADDAT2 every 48 s The previous conversion results are overwritten unless the contents are transferred to the memory by PEC...

Page 280: ...Value 0000H Bit Function FSADCDIFF Selects FSADC input range Selects input range of the Full Service ADC FSADCDIFF 0 single ended input FSDACDIFF 1 differential input ADWULE Defines threshold level fo...

Page 281: ...ronas ADDAT2 Reset Value 0000H Bit Function ADRESi 7 0 A D Conversion Result 8 bit of Channel 0 3 ANA 0 3 For each A D channel two successive 7 bit samples 33 3 MHZ are processed averaged and scaled t...

Page 282: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Peripherals 7 124 Micronas...

Page 283: ...Clock System...

Page 284: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Clock System 8 3 Micronas 8 Clock System...

Page 285: ...applications the timing reference given by the horizontal frequency of the CVBS signal can be used to measure the timing tolerance and to adjust the programming Figure 8 1 Clock System in M2 The on ch...

Page 286: ...runs the pixel clock fPIX which is programmable in a range of 10 50 MHz It serves the output part of the display FIFO and the D A converters The pixel clock is derived from the high frequency output...

Page 287: ...elation between the output pixel frequency and the frequency of the crystal The pixel frequency does not depend on the line frequency It can be calculated by the following formula The pixel frequency...

Page 288: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Clock System 8 8 Micronas...

Page 289: ...Sync System...

Page 290: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Sync System 9 3 Micronas 9 Sync System...

Page 291: ...on information from two independent pins which deliver separate horizontal and vertical signals Due to the not line locked pixel clock generation refer to Chapter 8 it can process any possible horizon...

Page 292: ...gs are independent of all other registers Screen Background Area The size of that area is defined by the sync delay registers SDH and SDV and the size of pixel layer1 The contents of that area are def...

Page 293: ...rtical interrupt to the controller to support the recognition of the frequencies of an external sync source e g a VGA source via SCART These interrupts are related to the positive edge of the non dela...

Page 294: ...t pin V Master mode only 0 At pin V the vertical sync appears 1 At pin V a composite sync signal including equalizing pulses H Sync and V Syncs is generated VCS The length of the equalizing pulses hav...

Page 295: ...horizontal sync edge The phase relation between V and H differs from application to application To guarantee vertical jitter free processing of external sync signals the vertical sync impulse can be d...

Page 296: ...es If a non interlaced picture with 312 lines should be generated set this register to 312 and set the interlace bit to 1 The hardware will generate a vertical impulse every 312 lines Progressive timi...

Page 297: ...s register defines the delay in lines from the vertical sync to the first line of pixel layer 1 on the screen Bit Function SDH 11 0 Horizontal Sync Delay Master and slave mode This register defines th...

Page 298: ...he positive edge of the horizontal sync impulse normal polarity is assumed The beginning of the clamp phase can be calculated by the following formula tH_clmp_b 480 ns BHC EHCR 7 0 End of Horizontal C...

Page 299: ...ion BVCR 9 0 Beginning of Vertical Clamp Phase Master and slave mode This register defines the beginning of the vertical clamp phase from the positive edge of the vertical sync impulse at normal polar...

Page 300: ...al Clamp Phase Master and slave mode This register defines the end of the vertical clamp phase from the positive edge of the vertical sync impulse at normal polarity in line count Note It must be guar...

Page 301: ...Display Generator...

Page 302: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Display Generator 10 3 Micronas 10 Display Generator...

Page 303: ...g bitmap information in various formats together with attributes which define the final behavior of those bitmaps Depending on these attributes these bitmaps are processed and written into the frame b...

Page 304: ...n be positioned relative to layer 1 also in negative direction If layer 2 exceeds the dimensions of layer 2 these exceeding parts are not visible on the screen The alignment of the OSD on the screen d...

Page 305: ...tem and Clock System In the area which is defined for layer 1 or layer 2 layer area each pixel is defined by the attribute definition of the frame buffer There is no pixel by pixel definition for the...

Page 306: ...2 is performed by the display generator As a result of the RGB output of M2 there is only one RGB stream which contains the information of layer 1 and layer 2 This RGB stream is externally mixed with...

Page 307: ...In overlapped layer mode a transparency hierarchy is defined for layer 2 layer 1 screen background and video The transparency hierarchy is controlled for each pixel by two bits TR1 0 which are define...

Page 308: ...n a 0 0 0 Back ground Back ground X 2 X 0 0 0 0 0 Layer 2 Layer 2 X X 0 1 0 Meshed 0 Layer 2 Layer 2 Video 0 0 1 X 0 0 0 Layer 1 Layer 1 0 1 1 X 0 Meshed 0 Layer 1 Layer 1 Video 1 0 1 X 0 0 0 Back gro...

Page 309: ...r 1 is read As a result in the area of layer 2 the pixel information for layer 1 is not available This is why layer 2 is transparent to video and not to layer 1 As a result in embedded layer mode tran...

Page 310: ...screen background Depending on the transparency bits of one of the layers subsequent signals are switched to RGB COR and BLANK normal polarity assumed The output signals of M2 COR BLANK RGB depend onl...

Page 311: ...ground 1 1 n a n a 0 0 0 Back ground Back ground n a n a 0 0 0 0 0 Layer 2 Layer 2 n a n a 0 1 0 Meshed 0 Layer 2 Layer 2 Video n a n a 1 0 0 0 0 Back ground Back ground n a n a 1 1 0 0 0 Back ground...

Page 312: ...ts in Background Area Screen Background BLANK Pin COR Pin RGB Pins RGB Tube STR1 STR0 0 0 0 0 RGB values defined in SAR RGB values defined in SAR 0 1 Meshed 0 RGB values defined in SAR RGB values defi...

Page 313: ...t to the destination memory area Different input and output formats are supported Note 1 The 2 bit format is defined as a format for the frame buffer but not supported by the GA Table 10 4 Overview on...

Page 314: ...3 Pixel UED11175 Memory Addr n 2 Memory Addr n 13 Bit1 Pixel Pixel 12 Bit0 Pixel 12 Bit1 Pixel 13 Bit0 Pixel 14 Bit1 Pixel 14 Bit0 Pixel 15 Bit1 Pixel 15 Bit0 Pixel 8 Bit1 Pixel 8 Bit0 Pixel 9 Bit1 Pi...

Page 315: ...or the 16 bit information is bypassing CLUT2 The 5 6 5 format always bypasses CLUT2 Figure 10 9 Overview on SRU UED11177 Memory Addr n 2 Memory Addr n 3 Bit5 Pixel Pixel 3 Bit6 Pixel 3 Bit7 Pixel 3 Bi...

Page 316: ...Pixel Format Using this format the frame buffer contains colour vectors These 8 bitplane colour vectors will be converted into 4 4 4 2 format R G B transparency value by CLUT2 Figure 10 11 8 bit Pixel...

Page 317: ...Flash Flash can be disabled if both 5 bit colour vectors point to the same CLUT2 location Inverted Flash Inverted flash is supported by exchanging the FlashC vector with the Pixel vector UED11181 M TR...

Page 318: ...e 12 bit RGB value and the 2 bit transparency information is directly fed into the D A converter and the BLANK COR pins Frame Buffer in 16 bit Pixel Format 5 6 5 In this mode the frame buffer contains...

Page 319: ...e 10 15 Overview of GA 10 5 1 Transfer Modes Different transfer modes are available The table below shows all possible combinations of input and output formats Transparency available means that if tra...

Page 320: ...0000 IN 0 11 0 00010 1 bit bitmap 8 bit No OUT 7 0 CLUT1 0000000 IN 0 7 0 00011 1 bit bitmap 16 bit 5 6 5 No OUT 15 0 CLUT1 0000000 IN 1 0 15 0 00100 2 bit bitmap 16 bit TTX No OUT 15 0 OUT 14 13 FLA...

Page 321: ...bitmap 16 bit 4 4 4 2 Yes OUT 15 1 OUT 14 13 CLUT1 0000000 IN 7 0 14 13 OUT 12 IT OUT 11 0 CLUT1 0000000 IN 7 0 11 0 01110 8 bit bitmap 8 bit No OUT 7 0 CLUT1 IN 7 0 7 0 01111 8 bit bitmap 16 bit 5 6...

Page 322: ...o the last address is automatically added This feature can be used if an array of data has to be copied from one memory location into another bigger array at any other memory location The linear addre...

Page 323: ...th less than a byte Group 2 formats are formats which define each pixel by 8 bits and group 3 formats are formats which define each pixel by 16 bits Group 1 In 1 bit bitmap 2 bit bitmap and 4 bit bitm...

Page 324: ...g a memory transfer these clipped memory areas are excluded from the transfer The table below describes the settings and the corresponding GAIs with the affected bit positions inside the GAI Used GAI...

Page 325: ...dth of the destination in count of pixels and not in bytes So for output formats of group 1 the memory area which is described by a HEIGHT_OUT value and a WIDTH_OUT value needs the double amount of me...

Page 326: ...FSET have to be adapted by the software to get a complete character Clipping is not affected by TDH and TDW The following table is an example of a 1 bit bitmap 30 50 which should be transferred either...

Page 327: ...chosen only the destination area not the source area is affected The following two figures explain the different representation of pixels in the frame buffer in non italic and italic mode Figure 10 1...

Page 328: ...e Buffer Next to the destination pixel offset from line to line the italic bit I alternates from line to line This italic bit is used to control the D A converter to realize a horizontal line alternat...

Page 329: ...d executing all GAIs the GA gives the controller an interrupt GAFIR Note GPRGCRH GPRGCRL and DGCON are the only special function registers to control the display generator GAIs described in the next p...

Page 330: ...SCR 1 The outputs have the function according to the specifications described in the following paragraphs Note The SRU registers FBR and DBR have to be programmed with a valid memory address before en...

Page 331: ...XDEL Reset Value 0000H Bits set to 00 no delay 01 delay of 1 pixel clock cycle 10 delay of 2 pixel clock cycles 11 reserved The reset value of PXDEL is set to 0000H which means no dely of the SRU outp...

Page 332: ...he organization of GAIs in the memory Figure 10 21 Organization of GAIs in the External SDRAM UED11190 Byte Address n 3 k Byte Address n 2 k Byte Address n 1 k Byte Address n k GAI No k GAI No GAI No...

Page 333: ...d by the GA during the vertical sync area If such a GA instruction is read by the GA outside the V sync area it waits until the next V sync appears Note The V sync area is defined for that purpose as...

Page 334: ...tributes SAR Bit Function SBTL Screen Background Transparency under Layer Area Defines whether the screen background area is transparent under a layer 1 2 area or not 0 The screen background within a...

Page 335: ...height 1 Double height The contents of the screen are stretched in vertical direction The SRU repeats the same pixel information twice in vertical direction Note DDH 1 the frame buffer height HEIGHT_L...

Page 336: ...it Layer 2 switched off 0010 16 bit 5 6 5 Layer 2 switched off 0011 Layer 1 2 switched off 0100 reserved 0101 reserved 0110 16 bit 4 4 4 2 or TTX 2 bit overlapped 0111 reserved 1000 16 bit 4 4 4 2 or...

Page 337: ...nction HEIGHT_L1 9 0 Height of Frame Buffer 1 The height of the frame buffer can vary between 0 HEIGHT_L1 0 d and 1023 pixels HEIGHT_L1 1023 d WIDTH_L1 10 0 Width of Frame Buffer 1 The width of the fr...

Page 338: ...The height of layer 2 can vary between 0 HEIGHT_L2 0 d and 1023 pixels HEIGHT_L2 1023 d WIDTH_L2 10 0 Width of Layer 2 The width of the layer 2 can vary between 0 WIDTH_L2 0 d and 2046 pixels WIDTH_L...

Page 339: ...f layer 1 Negative coordinates are also supported so it is also possible to move a layer 2 window from the top or left side of a layer 1 window DCR Bit Function ULY 10 0 Upper left corner Y coordinate...

Page 340: ...f 1 line Next to the start address height and width a clipping offset must be given for clipping For a rectangle clipping area the sum of this clipping offset and the clipping width must be the same a...

Page 341: ...GHT_CLIP 0d and 1023 pixels HEIGHT_CLIP 1023d C_OFFSET 10 4 Clipping Offset Bit 10 4 The LSBs of C_OFFSET are defined by instruction CUR WIDTH_ CLIP 10 0 Width of the clipping area The width of the cl...

Page 342: ...on Otherwise this bit must be set to 0 S_ADDR 23 0 Start address of memory area to be transferred Bit 23 0 of a byte address Bit Function GO Must be set to 1 if GA is to start memory transfer after ex...

Page 343: ...width and height of the source of the transfer area Please also refer to Chapter 10 5 2 TSR Bit Function GO Must be set to 1 if GA is to start memory transfer after executing this GA instruction Othe...

Page 344: ...r executing this GA instruction Otherwise this bit must be set to 0 HEIGHT_ OUT 9 0 Height of the transferred area in count of pixels HEIGHT_OUT 0 No transfer will be executed WIDTH_ OUT 10 0 Width of...

Page 345: ...emory transfer after executing this GA instruction Otherwise this bit must be set to 0 S_OFFSET 10 0 Source offset value for non linear transfer For more information about S_OFFSET refer to Chapter 10...

Page 346: ...is filled with a constant CLUT1 input vector 0 of CLUT1 instead of the source bitmap input CL 1 0 Clipping on off 00 Clipping is switched off 01 Reserved 10 Clipping is switched on Pixels within the c...

Page 347: ...dth during Transfer 0 Normal width is selected 1 The memory transfer is stretched in horizontal direction on the output side TDH Double Height during Transfer 0 Normal height is selected 1 The memory...

Page 348: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Display Generator 10 50 Micronas...

Page 349: ...D A Converter...

Page 350: ...s a 3 6 bit voltage D A converter to generate analog RGB output signals with a nominal amplitude of 0 7 V also available 0 5 V 1 0 V and 1 2 V peak to peak Two different modes are available in order t...

Page 351: ...djustment of RGB Converter The user can change the output gain of the DAC 00 0 5 V 01 0 7 V 10 1 0 V 11 1 2 V BWC Bandwidth Control 0 The effective bandwidth of the DAC is set to 50 MHz 1 The effectiv...

Page 352: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 D A Converter 11 6 Micronas...

Page 353: ...Slicer and Acquisition...

Page 354: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Slicer and Acquisition 12 3 Micronas 12 Slicer and Acquisition...

Page 355: ...of WSS data Both CVBS inputs contain an on chip clamping circuit The integrated A D converters are 7 bit video converters running at the internal frequency of 33 33 MHz The sliced data is synchronize...

Page 356: ...Micronas 12 2 Slicer Architecture The slicer is composed of five main blocks The full service slicer Slicer 1 The WSS only slicer Slicer 2 The H V synchronization for full service slicer Sync 1 The H...

Page 357: ...Separation Data Slicer 2 WSS only Slicer Sync 2 H PLL Timing Sync H V Sep CVBS2 HS2_IR VS2_IR Sync 1 Sync Timing Sep H V H PLL CC_IR L23_IR HS1_IR VS1_IR Acquisition Interface Full Service Slicer Sli...

Page 358: ...tortion Both flags can be used to optimize the correcting circuit characteristic in order to achieve best reception performance Frequency Attenuation During signal transmission the CVBS can be attenua...

Page 359: ...ing CRI using the transitions in the sliced data stream For TV mode this D PLL is also frozen after CRI during VCR mode it is tuned throughout the line using a slow time constant Timing informations f...

Page 360: ...lses are fed into a digital H PLL which has flywheel functionality The H PLL includes a counter which is used to generate all the necessary horizontal control signals The vertical sync is used to sync...

Page 361: ...irst one is 8 bit wide and is loaded down with the field parameters The second one is 16 bit wide and fixed to the FC of VPS The third one is also 16 bit wide but can be loaded with the field paramete...

Page 362: ...rameters for configuration and they produce status information for the CPU Some of these parameters and status bits are constant for a field Those parameters are called field parameters They are downl...

Page 363: ...yte 1 Data byte 3 Data byte 2 Data byte 5 Data byte 4 Empty Empty Empty Empty Empty Empty Line Parameters for Slicer 1 Line Parameters for Slicer 1 Line Status 1 of Line 7 Data Data Data Data Data Dat...

Page 364: ...00H Bit Function ACQON Enable Acquisition 0 The ACQ interface does not access memory immediately inactive 1 The ACQ interface is active and writes data to memory switching on is synchronous to V VBIAD...

Page 365: ...pt 1 Enables the interrupt VS2_IR VS interrupt The vertical sync impulse can be used to have field synchronization for the software VS of slicer 2 is used 0 No request pending 1 This source has raised...

Page 366: ...field parameters are updated even if only one of the two CVBS signals has a valid sync timing So it is assured that even if CVBS1 is not available data of CVBS2 still can be sliced ACQFP0 Reset Value...

Page 367: ...Version 2 1 Slicer and Acquisition 12 16 Micronas Bit Function FC3MASK 15 0 Mask for Framing code 3 Bit 15 Mask for first received bit of FC Bit 0 Mask for last received bit of FC 5 4 3 2 1 0 11 10 9...

Page 368: ...AFRON Automatic frequency depending attenuation compensation 0 Automatic compensation Off 1 Automatic compensation On Automatic measurement depending compensation ANOON Automatic noise compensation 0...

Page 369: ...the same as in last slicer 1 field 1 New WSS data from slicer 2 received WSS2_ DATA 83 80 4 bits of sliced data of slicer 2 WWS2_DATA 83 first received bit written to memory by ACQ interface Note See...

Page 370: ...ACQFP4 ACQFP6 to ACQFP8 Bit Function WSS2_ DATA 47 32 16 bits of sliced data of slicer 2 written to memory by ACQ interface Note See also ACQFP3 to ACQFP5 and ACQFP7 to ACQFP8 Bit Function WSS2_ DATA...

Page 371: ...by ACQ interface FIELD1 status bit 0 Actual field of slicer 1 is field 1 1 Actual field of slicer 1 is field 2 Written to memory by ACQ interface FREATTF status bit Frequency depending attenuation mea...

Page 372: ...itive 1 If group delay distortion has been detected it was negative Written to memory by ACQ interface CVBS input of slicer 1 is used STAB2 status bit 0 H PLL of slicer 2 not locked 1 H PLL of slicer...

Page 373: ...H Bit Function DINCR 15 0 Specifies the frequency of the D PLL of slicer 1 This parameter is used to configure the D PLL output frequency according to the service used DINCR fdata 218 33 33 MHz fdata...

Page 374: ...n detected during automatic mode or if the bit NOION has been set a special low pass can be switched into the signal pass by setting this bit useful if mainly high frequency noise above 3 5 MHz is pre...

Page 375: ...ority are 1 a 1 is sliced otherwise a 0 MLENGTH specifies how many samples are taken MLENGTH Number of samples 000 1 001 3 010 5 011 7 100 9 101 11 110 13 111 15 ALENGTH 1 0 If noise has been detected...

Page 376: ...This can be done by using different clocks for the filter The filter itself shows sufficient suppression for frequencies between 0 0757 SLCLK and 0 13 SLCLK SLCLK is the actual filter clock and corres...

Page 377: ...s stopped after CRI H PLL slow time constant 1 D PLL is tuned throughout the line H PLL fast time constant Bit Function SLSS Slicing Level Source Selector The slicer allows the use of an internal calc...

Page 378: ...can be set for the following fields by writing to parameter SSL PERRP 5 0 Phase Error Watch Dog Preliminary detection of test line CCIR331a or b The value shows how often in a line the internal PLL fo...

Page 379: ...IR331a or b This is the exact phase error watch dog output for the current line The value shows how often in a line the internal PLL found strong phase deviations between PLL and sliced data The value...

Page 380: ...0 FREON 0 0 0 0 0 PFILON 0 1 1 1 1 LOWPON 0 1 1 1 1 PLLTON 0 1 1 1 1 ACCUON 0 1 1 1 1 NOION 0 0 0 0 0 FULL 0 0 0 0 0 DINCR 54559 45041 39321 7864 7920 FC1ER 0 0 0 0 0 MLENGTH 1 2 7 7 7 ALENGTH 2 2 2...

Page 381: ...Register Overview...

Page 382: ...chapters to describe the functionality of the SFRs Display generators and slicers are mainly programmed via RAM registers which are not mentioned in this chapter due to their variable position in the...

Page 383: ...set Value H REG_NAME Name of this register Register contents after reset 0 1 defined value X undefined after power up Bits that are set cleared by hardware are marked with a shaded access box r Read o...

Page 384: ...neral Purpose Word Register R0 XXXXH R1 CP 2 F1H CPU General Purpose Word Register R1 XXXXH R2 CP 4 F2H CPU General Purpose Word Register R2 XXXXH R3 CP 6 F3H CPU General Purpose Word Register R3 XXXX...

Page 385: ...RH2 CP 5 F5H CPU General Purpose Byte Register RH2 XXH RL3 CP 6 F6H CPU General Purpose Byte Register RL3 XXH RH3 CP 7 F7H CPU General Purpose Byte Register RH3 XXH RL4 CP 8 F8H CPU General Purpose By...

Page 386: ...ister F0B8H 5CH 0000H S0ABCON Autobaud Control Register F1B8H DCH 0000H S0BG Baud Rate Timer Reload Register FEB4H 5AH 0000H S0FDV Fractional Divider Register FEB6H 5BH 0000H S0PMW IrDA Pulse Mode and...

Page 387: ...000H RTCL Count Register Low Word F0D4H 6AH 0000H RTCH Count Register High Word F0D6H 6BH 0000H RTCRELL Reload Register Low Word F0CCH 66H 0000H RTCRELH Reload Register High Word F0CEH 67H 0000H RTCIS...

Page 388: ...Channel 3 and 4 FEA2H 51H 0000H ADCCON ADC Control Register FEA4H 52H 0000H Interrupt Control Registers T2IC Timer 2 Interrupt Control Register FF60H B0H 0000H T3IC Timer 3 Interrupt Control Register...

Page 389: ...IC ASC Autobaud Start Interrupt Control FF9EH CFH 0000H I2 CTIC I2 C Transfer Interrupt Control F194H CAH 0000H I2 CPIC I2 C Protocol Interrupt Control F18CH C6H 0000H I2 CTEIC I2 C Transmission End I...

Page 390: ...gister FEDEH 6FH 0000H CLISNC PEC Channel Link Interrupt Subnode Register FFA8H D4H 0000H Port Registers RP0H Reset Configuration at Port 4 read only F108H 85H XXH P2 Port 2 Register FFC0H E0H 0000H P...

Page 391: ...ntal Clamping Register F1B2H D9H 1400H PFR Pixel Frequency Register F1B6H DBH 00A4H DACCON RGB DAC Control Register F1B4H DAH 0005H External Bus Interface Control Registers REDIR Memory Map Redirectio...

Page 392: ...CH D6H 0000H ADDRSEL1 Address Select Register 1 FE18H 0CH 0000H ADDRSEL2 Address Select Register 2 FE1AH 0DH 0000H ADDRSEL3 Address Select Register 3 FE1CH 0EH 0000H ADDRSEL4 Address Select Register 4...

Page 393: ...E06H 03H 0003H MDH CPU Multiply Divide Control Register High Word FE0CH 06H 0000H MDL CPU Multiply Divide Control Register Low Word FE0EH 07H 0000H MDC CPU Multiply Divide Control Register FF0EH 87H 0...

Page 394: ...F07CH 3EH XXXXH TM_LO Hardware Testmode Register Low FEFCH 7EH 0000H TM_HI Hardware Testmode Register High FEFEH 7FH 0000H FOCON SCU Register no Function within M2 FFAAH D5H 0000H SYSCON3 SCU Register...

Page 395: ...ss The following tables summarize the register symbols and their short addresses The physical address can be calculated by multiplying the short address by 2 and adding that value to FE00H for the SFR...

Page 396: ...ECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 68H PECSN0 PECSN1 PECSN2 PECSN3 PECSN4 PECSN5 PECSN6 PECSN7 70H 78H BVCR EVCR DGCON TM_LO TM_HI 80H BUSCON0 MDC 88H PSW SYSCON BUSCON1 BUSCON2 BUSCON3 BU...

Page 397: ...LS reserved RTCRELL RTCRELH 68H T14REL T14 RTCL RTCH reserved reserved DCMPLL DCMPLH 70H DCMPGL DCMPGH DCMP0L DCMP0H DCMP1L DCMP1H DCMP2L DCMP2H 78H DTREVT DSWEVT DEXEVT DBGSR 80H RP0H 88H XBCON1 XBCO...

Page 398: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Register Overview 13 20 Micronas...

Page 399: ...Elelctrical Characteristics...

Page 400: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Electrical Characteristics 14 3 Micronas 14 Electrical Characteristics...

Page 401: ...nces not even momentarily and individually as permanent damage to the IC will result Table 14 1 Ambient Temperature TA 0 C 70 C Parameter Symbol Limit Values Unit Test Condition min max Supply voltage...

Page 402: ...functions given in the circuit description are fulfilled Table 14 2 Operating Range Parameter Symbol Limit Values Unit Test Condition min max Ambient temperature TA 0 70 C Supply voltage 3 3 V VDD33...

Page 403: ...e mode supply current with A D wake up RTC and External Interrupts in active state IIDLE 12 mA Analog and digital supply Sleep mode supply current RTC running ISLEEP 1 2 mA Analog and digital supply P...

Page 404: ...A at Pins CVBSi CDec_CPL nF CVBS Input CVBS1A ADC_DIFF 1 non differential CVBS Input Pin capacitance CP pF Input impedance ZP 1 M Ext coupling capacitance CCPL1 10 100 nF Source impedance 500 Overall...

Page 405: ...sistance RL 10 k Diff non linearity 0 5 0 5 LSB Int non linearity 0 5 0 5 LSB Output current tracking 3 Skew to COR Blank tskew 5 5 ns Jitter to Horizontal Sync Reference tJit 4 ns Address Bits A0 to...

Page 406: ...Output Fall Time tf 2 ns 10 90 Load Capacitance CL 20 pF BLANK CORBLA Output Rise Time tr 8 12 5 ns 10 90 Output Fall Time tf 8 12 5 ns 10 90 Load Capacitance CL 20 pF BLANK CORBLA Control bit CORBL 0...

Page 407: ...5 pF VSYNC Input Rise Time tr 200 ns 10 90 Input Fall Time tf 200 ns 10 90 Input Hysteresis VHYST 300 600 mV Input Pulse Width TIPWV 2 fh Output Pulse Width TIPWV 1 fH Depends on Register HPR Output...

Page 408: ...4 Io 8 mA Hysteresis Voltage I2 C Inputs P6 5 P6 6 P6 7 P3 0 P3 1 UHSYT 100 mV A D Converter Characteristics Port 5 0 to P5 3 Input Voltage Range Vain 0 2 5 V ADC Resolution RES 8 BIT binary Output du...

Page 409: ...nc Timing Sync master mode Figure 14 2 VCS Timing Sync master mode UET11193 HSYNC VSYNC OPWH t OPWV t Line i Line i 1 Line i 2 UET11194 CS V Equalizing Pulses Field Sync Pulses Equalizing Pulses Horiz...

Page 410: ...haracteristics 14 13 Micronas 14 5 Package Outlines P MQFP 128 2 Plastic Metric Quad Flat Package GPM09233 Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package...

Page 411: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Electrical Characteristics 14 14 Micronas...

Page 412: ...ity for patent infringements or other rights of third parties which may result from its use Further Micronas GmbH reserves the right to revise this publication and to make changes to its content at an...

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