Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 84 Micronas
Figure 7-38 SFRs and Port Pins Associated with the SSC0
The SSC0 supports full-duplex and half-duplex synchronous communication up to
16.5 MBaud (@ 33.33 MHz module clock). The serial clock signal can be generated by
the SSC0 itself (master mode), or received from an external master (slave mode). Data
width, shift direction, clock polarity and phase are programmable. This allows
communication with SPI-compatible devices. Transmission and reception of data is
double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial
clock signal.
The high-speed synchronous serial interface can be configured in a very flexible way, so
it can be used with other synchronous serial interfaces, serve for master/slave or
multimaster interconnections or operate compatible with the popular SPI interface. So it
can be used to communicate with shift registers (I/O expansion), peripherals (e.g.
EEPROMs etc.) or other controllers (networking). The SSC0 supports half-duplex and
full-duplex communication. Data is transmitted or received on pins MTSR0 (Master
Transmit/Slave Receive) and MRST0 (Master Receive/Slave Transmit). The clock signal
is output or input on pin SCLK0. These pins are alternate functions of port pins.
P3
SSCCON
SSCRIC
SSCEIC
SSCRB
Port 3 Direction Control Register
SSC Transmit Buffer Register (write only)
SSC Transmit Interrupt Control Register
Port 3 Open Drain Control Register
SSC Baud Rate Generator/Reload Register SSCBR
SSCTB
SSCTIC
ODP3
DP3
SSC Receive Interrupt Control Register
SSC Error Interrupt Control Register
SSC Receive Buffer Register (read only)
SSC Control Register
Port 3 Data Register
UEA11157
Control Registers Ports & Direction Control
MTSR/P3.9
MRST/P3.8
SLCK/P3.13
P3
DP3
ODP3
Alternate Functions
SSCBR
SSCTB
SSCRB
Data Registers
SSCCON SSCTIC
SSCEIC
SSCRIC
Interrupt Control