Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 119 Micronas
Synchronization
In Mastermode, the SCL line is controlled by the I
2
C Module. Sent and received data is
only valid if SCL is high. With SCL going down, all modules are starting to count down
their low period. During the low period all connected modules are allowed to hold SCL
low. As the physical bus connection is wired-AND, SCL will remain low until the device
with the longest low period enters high state. Then the device with the shortest high
period will pull SCL low again.
Programming
It is strictly recommended not to write to the I
2
C registers when the I
2
C is working, except
for interrupt handling. This is indicated by the BUM bit (in master mode) and the interrupt
flags. All registers can be written in initial mode. In master mode the I
2
C is working as
long as the BUM bit is set, in slave mode the I
2
C is working from receiving a start
condition until receiving the next stop condition. Change of transmit direction is possible
only after a protocol interrupt (IRQP) or in initialization mode (MOD = 00
B
).
Initialization
Before data can be sent or received, data buffer size must be set in the count registers
(only necessary if buffer greater than one byte is available). To decide if slave/master or
multimaster mode is required, the MOD bits must be programmed.
Repeated Start Condition
The RSC bit must be set to one.
Start Condition
To generate a start condition the I
2
C must be in master mode. If the BUM bit is set, a
start condition is sent and the transmission started. The slave returns the acknowledge
bit, which is indicated by the LRB bit.
Sending Data Bytes
To send bytes it is only necessary to write data bytes to the transmit buffer every time a
data interrupt (IRQD) occurs.
Stop Condition
The BUM bit must be set to zero, or the STP bit must be set to one.
Receiving Data Bytes
To receive bytes it is necessary to set the TRX bit to zero. The bytes can be read after
every data interrupt (IRQD). After a stop condition (protocol interrupt IRQE), the count