Micronas SDA 6000, User Manual

Page: 247 / 412

SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 89 Micronas
the slave device from which it expects data either by separate select lines, or by
sending a special command to this slave.
After performing all necessary initializations of the SSC0, the serial interfaces can be
enabled. In a master device, the alternate clock line will now go to its programmed
polarity. The alternate data line will go to either ‘0’ or ‘1’, until the first transfer starts. After
a transfer, the alternate data line will always remain at the logic level of the last
transmitted data bit.
When the serial interfaces are enabled, the master device can initiate the first data
transfer by writing the transmit data into register SSCTB. This value is copied into the
shift register (which is assumed to be empty at this time), and the selected first bit of the
transmit data will be placed onto the MTSR line on the next clock to the baud rate
generator (transmission only starts, if SSC0EN = ‘1’). Depending on the selected clock
phase, a clock pulse will also be generated on the SCLK line. With the opposite clock
edge the master simultaneously latches and shifts in the data detected at its input line
MRST. This ‘exchanges’ the transmit data with the receive data. Since the clock line is
connected to all slaves, their shift registers will be shifted synchronously with the
master’s shift register, shifting out the data contained in the registers, and shifting in the
data detected at the input line. After the pre-programmed number of clock pulses (via the
data width selection) the data transmitted by the master is contained in all slaves’ shift
registers, while the master’s shift register holds the data of the selected slave. In the
master and all the slaves, the content of the shift register is copied into the receive buffer
SSCRB and the receive interrupt line SSC0RIR is activated.
A slave device will immediately output the selected first bit (MSB or LSB of the transfer
data) at pin MRST, when the content of the transmit buffer is copied into the slave’s shift
register. It will not wait for the next clock from the baud rate generator, as the master
does. The reason for this is that, depending on the selected clock phase, the first clock
edge generated by the master may be already used to clock in the first data bit. So the
slave’s first data bit must already be valid at this time.
Note: On the SSC0 a transmission and a reception always takes place at the same time,
regardless whether valid data has been transmitted or received.
The initialization of the SCLK pin on the master requires some attention in order to
avoid undesired clock transitions, which may disturb the other receivers. The state of the
internal alternate output lines is ‘1’ as long as the SSC is disabled. This alternate output
signal is ANDed with the respective port line output latch. Enabling the SSC with an idle-
low clock (SSC0PO = ‘0’) will immediately drive the alternate data output and (via the
AND) the port pin SCLK low. To avoid this, the following sequence should be used:
• select the clock idle level (SSC0PO = ‘x’)
• load the port output latch with the desired clock idle level
• switch the pin to output
• enable the SSC0 (SSC0EN = ‘1’)
• if SSC0PO = ‘0’: enable alternate data output