Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 107 Micronas
7.5.4 Registers
All available module registers are summarized in the overview table below.
I
2
C Configuration Register
ICCFG Reset Value: 0000
H
Register
Name Register Description Address b/p
1)
1)
b : b it addressable / p : bit p rotected
Reset Value
ICCFG I
2
C Configuration Register 00’E810
H
b 0000
H
ICCON I
2
C Control Register 00’E812
H
b 0000
H
ICST I
2
C Status Register 00’E814
H
b 0000
H
ICADR I
2
C Address Register 00’E816
H
b 0000
H
ICRTBL I
2
C Receive/Transmit Buffer 00’E818
H
– 0000
H
ICRTBH I
2
C Receive/Transmit Buffer 00’E81A
H
– 0000
H
IICPISEL
2)
2)
Itus currently no function. Should be left on reset value.
I
2
C Port Input Select Register 00’E804
H
b 0000
H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRPL 0 0
SCL
EN1 SCL
EN0
0
SDA
EN2
SDA
EN1
SDA
EN0
Field Bits Type Value Description
SDAENx
(x = 2 … 0)
2 … 0 rw
0
1
Enable Input for Data Pin x
These bits determine to which pins the I
2
C data
line is connected.
SDA pin x is disconnected.
SDA pin x is connected with I
2
C data line.
SCLENx
(x = 3 … 0)
5 … 4 rw
0
1
Enable Input for Clock Pin x
These bits determine to which pins the I
2
C
clock line is connected.
SCL pin x is disconnected.
SCL pin x is connected with I
2
C clock line.
BRPL 15 … 8 rw – Baud rate Prescaler Low
Determines the 8 least significant bits of the 10
bit baud rate prescaler. (See BPRH in ICADR.)