Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Clock System
8 - 4 Micronas
8.1 General Function
The on-chip clock generator provides M2 with its basic clock signals. Its oscillator can
either run with an external crystal and appropriate oscillator circuitry (refer to “Application
Diagram”) or it can be driven by an external digital clock signal. For applications with low
accuracy requirements (RTC is not used) the external oscillator circuit can also be a
ceramic resonator. Depending on the absolute tolerance of the resonator the slicer may
not work correctly. Moreover the display timings and baud rate prescaler have to be
adapted in an appropriate way. In some applications the timing reference given by the
horizontal frequency of the CVBS signal can be used to measure the timing tolerance
and to adjust the programming.
Figure 8-1 Clock System in M2
The on-chip phase locked loop (PLL), which is internally running at 600 MHz, is fed by
the oscillator or can be bypassed to reduce the power consumption in idle and sleep
mode. If it is not required to wake up immediately from idle mode, the PLL can be
switched off by entering sleep-mode. The same oscillator is used to clock the built-in
RTC. (For a further description refer to
Chapter 7.2 .)
From the output frequency of the PLL three clock systems are derived:
3 MHz
300 MHz
DTO
SRU (part 2)
Display-FIFO
50 MHz
PIX
10 MHz
f
UES11167
DAC
6 MHz
XTAL2
XTAL1
OSC
÷ 2
PLL
200 MHz
( 3)
÷ 2
÷
÷ 6
µ
f
CPU
C-Periph.
Sync
Ports
Slicer
ADC
DG
EBI
CLUTs
100 MHz
EMI
66.7 MHz
f
3 MHz
33.33 MHz
C
µ
RTC