Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
C16X Microcontroller
4 - 32 Micronas
Instruction pipelining increases the average instruction throughput considered over a
certain period of time. In the following, any execution time specification of an instruction
always refers to the average execution time due to pipelined parallel instruction
processing.
Figure 4-11 Sequential Instruction Pipelining
Standard Branch Instruction Processing
Instruction pipelining helps to speed up sequential program processing. When a branch
is taken, the instruction which has been fetched in advance is usually not the instruction
which must be decoded next. Thus, at least one additional machine cycle is normally
required to fetch the branch target instruction. This extra machine cycle is provided by
means of an imported instruction (see
Figure 4-12 ).
Figure 4-12 Standard Branch Instruction Pipelining
If a conditional branch is not taken, there is no deviation from the sequential program
flow, and thus no extra time is required. In this case, the instruction following the branch
instruction will enter the decoding stage of the pipeline at the beginning of the next
machine cycle after decoding the conditional branch instruction.
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1
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2
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3
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4
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5
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6
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FETCH
DECODE
EXECUTE
WRITEBACK
1 Machine Cycle
Time
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DECODE
EXECUTE
WRITEBACK
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