Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 83 Micronas
7.4 High Speed Synchronous Serial Interface
• Master and slave mode operation
– Full-duplex or half-duplex operation
• Flexible data format
– Programmable number of data bits: 2 to 16 bit
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of SCLK
• Baud rate generation from 12.5 MBaud to 190.7 Baud (@ 25 MHz module clock)
• Interrupt generation
– on a transmitter empty condition
– on a receiver full condition
– on an error condition (receive, phase, baud rate, transmit error)
• Three pin interface
– Flexible SSC0 pin configuration
The High Speed Synchronous Serial Interface SSC0 provides serial communication
between M2 and other microcontrollers, microprocessors or external peripherals. It is
compatible with the SSC0 of the referred C161RI device with the following extensions:
• Maximum SSC clock in master mode:
f
SCLK max.

16.5 MHz.
Maximum SSC clock in slave mode: f
SCLK max.

8.25 MHz.
• Reload value 0000
H
is allowed in master mode.
• Because of the symmetric SSC clock requirement in master mode (50% duty cycle),
the divide-by-2 prescaler is required.
• The counter of the baud rate generator is only active (running) during a transmit or
receive operation.
• The transmit interrupt becomes active when a transmission starts.
The SSC0 registers can be basically divided into three types of registers as shown in
Figure 7-38 .