Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 15 Micronas
Note: Only state transitions of T3OTL which are caused by the overflows/underflows of
T3 will trigger the counter function of T2/T4. Modifications of T3OTL via software
will NOT trigger the counter function of T2/T4.
For counter operation, an external pin associated to line TxIN must be configured as
input. The maximum input frequency which is allowed in counter mode is
f
hw_clk
/8 (BPS1
= ‘01’). To ensure that a transition of the count input signal which is applied to TxIN is
correctly recognized, its level should be held for at least 4
f
hw_clk
cycles (BPS1 = ‘01’)
before it changes.
7.1.1.1 Timer Concatenation
Using the output toggle latch T3OTL as a clock source for an auxiliary timer in counter
mode concatenates the core timer T3 with the respective auxiliary timer. Depending on
which transition of T3OTL is selected to clock the auxiliary timer, this concatenation
forms a 32-bit or a 33-bit timer/counter.
• 32-bit Timer/Counter : If both positive and negative transitions of T3OTL are used to
clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core
timer T3. Thus, the two timers form a 32-bit timer.
• 33-bit Timer/Counter : If either a positive or a negative transition of T3OTL is selected
to clock the auxiliary timer, this timer is clocked on every second overflow/underflow
of the core timer T3. This configuration forms a 33-bit timer (16-bit core timer
+ T3OTL + 16-bit auxiliary timer).
The count directions of the two concatenated timers are not required to be the same.
This offers a wide variety of different configurations.
In this case T3 can operate in timer, gated timer or counter mode.
Table 7-6 Auxiliary Timer (Counter Mode) Input Edge Selection
T2I/T4I Triggering Edge for Counter Increment/Decrement
X 0 0 None. Counter Tx is disabled
0 0 1 Positive transition (rising edge) on TxIN
0 1 0 Negative transition (falling edge) on TxIN
0 1 1 Any transition (rising or falling edge) on TxIN
1 0 1 Positive transition (rising edge) of output toggle latch T3OTL
1 1 0 Negative transition (falling edge) of output toggle latch T3OTL
1 1 1 Any transition (rising or falling edge) of output toggle latch T3OTL