Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 85 Micronas
Figure 7-39 Synchronous Serial Channel SSC0 Block Diagram
The operating mode of the serial channel SSC0 is controlled by its bit-addressable
control register SSCC0N. This register serves two purposes:
• during programming (SSC0 disabled by SSC0EN = ‘0’) it provides access to a set of
control bits
• during operation (SSC enabled by SSC0EN = ‘1’) it provides access to a set of status
flags
The shift register of the SSC0 is connected to both the transmit pin and the receive pin
via the pin control logic (see block diagram in
Figure 7-39 ). Transmission and reception
of serial data is synchronized and takes place at the same time, e.g. the same number
of transmitted bits is also received. Transmit data is written into the Transmit Buffer
SSCTB. It is moved to the shift register as soon as this is empty. An SSC master
(SSC0MS = ‘1’) immediately begins transmitting, while an SSC slave (SSC0MS = ‘0’)
will wait for an active shift clock. When the transfer starts, the busy flag SSC0BSY is set
and a transmit interrupt request line (SSCTIR) will be activated to indicate that SSCTB
may be reloaded again. When the programmed number of bits (2 … 16) has been
UEB11158
16-Bit Shift Register
MRSTx
Internal Bus
Receive Buffer
Register SSC0RB
Transmit Buffer
Register SSC0TB
MTSRx
Pin
Control
SSC Control Block
SSC0CON
Status Control
SSC0EIR
SSC0TIR
SSC0RIR
Receive Int. Request
Transmit Int. Request
Error Int. Request
Control
Clock
Shift
Clock
Generator
Baud Rate
SCLKx
33 MHz